Publications Number 6500-1 5B
KIM-1
MICROCOMPUTER MODULE
USER MANUAL
AUGUST 1976
The information in this manual has been reviewed and is believed to be entirely reliable. However,
no responsibility is assumed for inaccuracies. The material in this manual is for informational
purposes only and is subject to change without notice.
Second Edition
© MOS TECHNOLOGY, INC. 1976
"All Rights Reserved"
MOS TECHNOLOGY, INC.
950 Rittenhouse Road
Norristown, PA 19401
TABLE OF CONTENTS
CHAPfitR 1
CHAFfER 2
CHAPTER 3
CHAPTER 4
CHAPTER 5
YOUR KIM-1 MICROCOMPUTER MODULE
GETTING STARTED
2.1 Parts Complement
2.2 A Few Words of Caution I
2.3 First Steps
2.4 Let's Try a Simple Problem
2.5 Adding an Audio Tape Unit
2.6 Adding a Teleprinter
THE KIM-1 SYSTEM
3.1 KIM-1 System Description
3.2 KIM-1 Memory Allocation
3.3 KIM-1 Operating Programs
OPERATING THE KIM-1 SYSTEM
4.1 Using the Keyboard and Display
4.2 Using the Audio Tape Unit
4.3 Using the Teleprinter
5
6
6
9
12
17
21
21
34
40
43
43
47
50
'S TRY A REAL APPLICATION
55
5.1
Defining the Interface
55
5.2
Writing the Program
58
5.3
Entering the Program
65
5.4
Executing the Program
66
5.5
Program Debugging and Modification
67
CHAPTER 6 EXPANDING YOUR SYSTEM 71
6.1 Memory and I/O Expansion 71
6.2 Interrupt Vector Management 75
CHAPTER? WARRANTY AND SERVICE 79
7.1 In-Warranty Service 79
7.2 Out-of-Warranty Service 80
7.3 Policy on Changes 80
7.4 Shipping Instructions 80
iii
LIST OF FIGURES
CHAPTER 2 2-1 KIM MODULE 7
2-2 Power Supply Connections 8
2-3 Audio Tape Unit Connections 13
2- 4 TTY Connections 18
CHAPTER 3 3-1 KIM-1 Block Diagram 24
3- 2 Detailed Block Diagram 25
3-3 Control and Timing 26
3-4 IK X 8 RAM Memory 27
3-5 Keyboard and Display 28
3-6 Keyboard Detail 29
3-7 TTY Interface 30
3-8 Audio Tape Interface 31
3-9 Application Connector 32
3-10 Expansion Connector 33
3-11 Memory Block Diagram 37
3-12 Memory Map 38
3-13 Special Memory Addresses 39
3-14 Flow Chart 41
CHAPTER 5 5-1 Speaker Application 57
5-2 Assembly Language Listing 60
5-3 Square Wave Output 62
5-4 Machine Language Code Table 63
5- 5 Key Sequence: Enter Program 65
CHAPTER 6 6-1 4K Expansion 73
6- 2 65K Expansion 74
6-3 Vector Selection 78
iv
LIST OF APPENDICES
APPENDIX A KIM-1 Parts List A-1
APPENDIX B KIM-1 Parts Location B-1
APPENDIX C In Case of Trouble C-1
APPENDIX D Suggested Power Supply D-1
APPENDIX E Audio Tape Format E-1
APPENDIX F Paper Tape Format F-1
APPENDIX G 6502 Characteristics G-1
APPENDIX H 6530 Characteristics H-1
APPENDIX I KIM-1 Program Listings I-l
V
CHAPTER 1
YOURKlM-1 MICROCOMPUTER MODULE
Congratulations and welcome to the exciting new world of micro-
computers I As the owner of a KIM-1 Microcomputer Module, you now have at
your disposal a completely operational, fully tested, and very capable
digital computer which incorporates the latest in microprocessor tech-
nology offered by MOS Technology, Inc. By selecting the KIM-1 module,
you have eliminated all of the problems of constructing and debugging a
microcomputer system. Your time is now available for learning the opera-
tion of the system and beginning immediately to apply it to your specific
areas of interest. In fact, if you will follow a few simple procedures
outlined in this manual, you should be able to achieve initial operation
of your KIM-1 module within a few minutes after unpacking the shipping
container.
Your KIM-1 module has been designed to provide you with a choice of
operating features. You may choose to operate the system using only the
keyboard and display included as part of the module. Next, you may add
a low cost audio cassette tape recorder to allow storage and retrieval
of your programs. Also, you may add a serial interfaced teleprinter to
the system to provide keyboard commands, hard-copy printing, and paper
tape read or punch capability.
1
At the heart of your KIM-1 system is an MCS 6502 Microprocessor
Array operating in conjunction with two MCS 6530 arrays. Each MCS 6530
provides a total of 102A bytes of Read-only Memory (ROM) , 64 bytes of
Random Access Memory (RAM), 15 Input/Output pins, and an Interval Timer.
Stored permanently in the ROM's of the MCS 6530 arrays are the monitor
and executive programs devised by MOS Technology, Inc. to control the
various operating modes of the KIM-1 system.
The KIM-1 system is intended to provide you with a capable micro-
computer for use in your "real-world" application. Accordingly, the
system includes a full 1024 bytes of RAM to provide data and program
storage for your application program. In addition, you are provided
with 15 bidirectional input/output pins to allow interface control of
your specific application. Finally, one of the interval timers included
in the system is available for generation of time base signals required
by your application.
Your KIM-1 system comes to you complete with all components mounted
and tested as a system. You need not worry about timing signals (we've
included a IMHz crystal oscillator on the module), interface logic or
levels between system components, or interface circuitry to peripheral
devices. In fact, you need only apply the indicated power supply voltages
to the designated pins to achieve full operation of your KIM-1 system.
We recommend that you read all of this manual before applying power
to or attempting to operate your KIM-1 module. In the order presented,
you will find:
Chapter 2 - "hints and kinks" to help you achieve initial
system operation
Chapter 3 - a more detailed description of the KIM-1 system
hardware and software
Chapter 4 - operating procedures for all system modes
Chapter 5 - an example of a typical application program
using all of the features of the KIM-1 system.
2
At some future time, you may find It desirable to expand the KIM-1
system to incorporate more memory, different types of memory, or addi-
tional input/output capability. Again, we have tried to make system
expansion as simple as possible with all required interface signals
brought out to a special connector on the module. Watch for:
Chapter 6 - a guide to system expansion for increasing
both memory and input/output capability
Despite our best efforts to provide you with a fully operable
and reliable system, you might encounter some difficulties with your
KIM-1 module. If so, refer to:
Chapter 7 - some guidance on warranty and service
procedures for your KIM-1 module
Following the basic text of this manual, you will find a series of
Appendices intended to provide you with detailed information on certain
specialized subjects of interest to you in understanding the operation
of the KIM-1 system.
Lastly, since this manual cannot presume to provide all of the
technical information on the hardware or programming aspects of the
MCS 6502 microprocessor array, we are including with your KIM-1 system
two additional manuals for your reference. The Hardware Manual defines
the various elements of the system, their electrical and interface
characteristics, and the basic system architecture and timing. The
Programming Manual provides the detailed information required to write
effective programs using the MCS 6502 instruction program set.
So much for introductory comments'. Now lets get started and see
if we can get your KIM-1 Microcomputer Module doing some real work for you.
3
CHAPTER 2
GETTING STARTED
This chapter is intended to guide you through the first important
steps in achieving initial operation of your KIM-1 Microcomputer Module.
We will ask you to perform certain operations without explanation at this
time as to why they are being done. In later sections of this manual,
full explanations will be offered for every operating procedure.
2. ; PARTS COMPLEMENT
After unpacking the shipping container for your KIM-1, you should
have located the following items:
3 Books - KIM-1 Users Manual
Hardware Manual
Programming Manual
1 Programming Card
1 System Schematic
1 KIM-1 Module
1 Connector (Already mounted on the Module)
1 Hardware Packet
1 Warranty Card
You may wish to save the shipping container and packing material
should you need to return your KIM-1 module to us at some future date.
5
2.2 A FEW WORDS OF CA UTION
WARNING
Your KIM-1 module includes a number of MOS integrated circuits. All such
circuits include protective devices to prevent damage resulting from
inadvertant application of high voltage potentials to the pins of the
device. However, normal precautions should be taken to prevent the appli-
cation of high voltage static discharges to the pins of an MOS device.
Immediately before removal of the packing material from your KIM-1 module,
you should develop the following precautionary habits:
1. Discharge any static charge build up on your body by touching a
ground connection before touching any part of your KIM-1 module.
(This precaution is especially important if you are working in a
carpeted area)
2. Be certain that soldering irons or test equipment used on the
KIM-1 module are properly grounded and not the source of
dangerously high voltage levels.
On a different subject, after unpacking your KIM-1 module, you will
note the presence of a potentiometer. This adjustment has been set at
the factory to insure correct operation of the audio cassette interface
circuits. It should never be necessary for you to change the position of
this potentiometer.
2.3 FIRSTSTEPS
After unpacking the KIM-1 module, locate the small hardware packet
and install the rubber pads provided. The rubber pads are located at the
bottom of the module (see attached sketch) and act both to lift the card
off your work surface and to provide mechanical support for the module
while you depress keys.
6
Place the module such that the keyboard is to your lower right and
observe that two connector locations extend from the module to your left.
The connector area on the lower left is referred to as the Application
connector (A) . You will note that a 44 pin board edge connector is
already installed at this location. The connector area to the upper
left is for use by you for future system expansion and is referred to
as the Expansion connector (E) .
Bl
lol
BOTTOM
VIEW
m
□□□
□□□□
□□□□
□□□□
□□□□
□□□□
TOP
VIEW
HM-l Module
FIGURE 2.1
7
Remove the (A) connector from the module and connect the pins as
shown in the sketch.
(A)
vcc
VBB
VSS
+ 5
Power Supply Connections
FIGURE 2.2
Reinstall the (A) connector making certain that the orientation is
correct .
Note 1: The +12 volt power supply is required only if you
will be using an audio cassette recorder in your system.
Note 2: The jumper from pin A-K to Vss (Pin A-1) is essential
for system operation. If you expand your system later,
this jumper will be removed and we'll tell you what to
do to pin A-K.
Note 3: If you don't have the proper power supplies already
available, you may wish to construct the low cost
version shown with schematic and parts list in
Appendix D. In any event, your power supply must
be regulated to insure correct system operation and
must be capable of supplying the required current
levels indicated in the sketch.
8
Now, recheck your connections, turn on your power supplies, and
depress (reset). You should see the LED display digits light
as your first check that the system is operational. If not, recheck
your hookup or refer to Appendix C (In Case of Trouble).
2. 4 LETS TRY A SIMPLE PR OGRAM
Assuming that you have completed successfully all of the steps thus
far, a simple program now can be tried to demonstrate the operation of
the system and increase your confidence that everything works properly.
We'll be using only the keyboard and display on the module for this
example. (In the next two sections we'll worry about the teleprinter
and the audio cassette).
For our first example, we will add two 8 bit binary numbers together
and display the result. We presume that you are familiar with the hex-
adecimal representation of numbers and the general rules for binary arith-
metic.
First check and be sure that the slide switch in the upper right
corner of the keyboard is pushed to the left (SST Mode is OFF) . Now
proceed with the following key sequence:
Press
Keys
See On Display
Step
! AD 1
xxxx
XX
1
I 1 I
olio
1 2 1
0002
XX
2
DA
0002
XX
3
1 1
I 8 1
0002
18
4
1 A
1 5 1
0003
A5
5
I + 1
1
1 1
0004
00
6
1 - !
I 6
1 5 1
0005
65
7
1 1 1
0006
01
8
m
1 8
0007
85
9
1 ^ 1
1 F
1 A 1
0008
FA
10
A
1 9 1
0009
A9
11
1 ^ 1
1
1 ° I
OOOA
00
12
I ^ 1
I 8
OOOB
85
13
1 P
1 B 1
OOOC
FB
14
I 4
c
OOOD
AC
15
I - 1
1 4
1 F 1
OOOE
4F
16
I ^ 1
1
1 c 1
OOOF
IC
17
9
What you have just done is entered a program and stored it in the
RAM at locations 0002 through OOOF. You should have noticed the purpose
of several special keys on your keyboard:
^'•'1 - selects the address entry mode
- selects the data entry mode
- increments the address without
changing the entry mode
[T1to[7]
- 16 entry keys defining the hex
code for address or data entry
You've noticed as well that your display contains 6 digits. The
four on the left are used to display the hex code for an address. The
two on the right show the hex code for the data stored at the address
shown. Therefore, when you pressed l'^^ I (step 1) and I ° I I ° 1 I ° I f"^
(step 2), you defined the address entry mode, selected the address 0002,
and displayed the address 0002 in the four left-most display digits.
Incidentally, when we show an "x" in the display chart, we mean that we
don't know what will be displayed and we "don't care."
Next you pressed I I (step 3) followed by CjH dU (step 4). Here,
you have defined the data entry mode and entered the value 18 to be
stored at your selected address 0002. Of course, the 18 then was dis-
played in the two right-most digits of your display.
You remained in the data entry mode but began to press I * I followed
by a two digit number (steps 5 to 17) . Note that each depression of the
key caused the address displayed to increase by one. The hex keys
following the I * I key continued to enter the data field of the display.
This procedure is merely a convenience when a number of successive address
locations are to be filled.
If you made any mistakes in pressing the keys, you should have noticed
that correcting an error is simply a matter of reentering the data until
the correct numbers show on the display.
10
The program you have entered is a simple loop to add two 8 bit
binary numbers together and present the result on the display. For a
programmer, the listing of the program entered might appear as follows:
POINTL
= $FA
POINTH
= $FB
START
= $1C4F
0000
VALl
0001
VAL2
0002
18
PROG
CLC
0003
A5
00
LDA VALl
0005
65
01
ADC VAL2
0007
85
FA
STA POINTL
0009
A9
00
LDA #00
OOOB
85
FB
STA POINTH
OOOD
4C
4F IC
JMP START
Stated in simple terms, the program will clear the carry flag (CLC),
load VALl into the accumulator (LDA VALl) , add with carry VAL2 to the
accumulator (ADC VAL2) , and store the result in a location POINTL (STA
POINTL). A zero value is stored in a location POINTH (LDA //00 and STA
POINTH) and the program jumps to a point labelled START (JMP START).
This pre-stored program will cause the display to be activated and will
cause the address field of your display to show the numbers stored in
locations POINTH and POINTL. Note that the result of the addition has
already been stored in location POINTL.
The hex codes appearing next to the address field of the listing are
exactly the numbers you entered to store the program. We refer to these
as machine language codes. For example, 4C is the hex code for the JMP
instruction of the microprocessor. The next two bytes of the program
define 1C4F (START) as the jump address.
As yet, you are not able to run the program because you have not yet
entered the two variables (VALl and VAL2). Lets try an actual example:
Press Keys See On Display Step />
r^Fl OOOF IC 17A
ro~i r~oi [ZD nn oofi xx i7b
Pda] Co] OOFl 00 18
OOFl 00 19
ro~i roi ro~i roi oooo xx 20
Cda] 0000 02 21
rui cn] 0001 03 22
nn \~Go] 0002 18 23
11
Steps 17A, 17B, and 18 insure that the binary arithmetic mode is
selected .
Steps 19 to 21 store the hex value 02 in location 0000 (VALl) . Step
22 stores the hex value 03 in location 0001 (VAL2) . Now we are ready to
run the program. In step 23, the I °°l key causes the program to execute
and the result, 05, appears in the right two digits of the address display.
Although the problem appears trivial, it illustrates the basic principles
of entering and executing any program as well as providing a fairly high
assurance level that your KIM-1 module is operating properly.
You should try one more example using your stored program. Repeat
steps 17A to 23 but substitute the value FF for VALl and VAL2 at locations
0000 and 0001. Now when you press the I "^^l key, your display should read:
OOFE XX
The answer is correct because:
FF = 1111 1111
+ FF = 1111 1111
FE 1111 1110
Try some more examples if you wish and then let's move on to the rest
of the system.
2. 5 ADDING A TAPE RECORDER
In the previous section, you entered and executed a program. If you
turn off the power supplies to the system, your program- is lost since the
memory into which you stored your program is volatile. If you require
the same program again, you would have to repower the system and reenter
the program as in the previous example.
The KIM-1 system is designed to work with an audio cassette tape
recorder/player to provide you with a medium for permanent storage of your
programs or data. The cassette with recorded data may be reread by the
system as often as you wish. In this section, you will connect the audio
cassette unit to the system and verify its operation.
12
The recording technique used by the KIM-1 system and the interface
circuits provided have been selected to insure trouble-free operation
with virtually any type and any quality level audio cassette unit. (We
have demonstrated correct operation with a tape unit purchased for less
than $20.00 from a local discount outlet). In addition, tapes recorded
on one unit may be played back to the system on a different unit if
desired. We recommend, of course, that you make use of the best equip-
ment and best quality tapes you have available.
In selecting a tape unit for use with your KIM-1 system, you should
verify that it comes equipped with the following features :
1. An earphone jack to provide a source of recorded
tape data to the KIM-1 system.
2. A microphone jack to allow recording of data from
the KIM-1 system on the tape.
3. Standard controls for Play, Record, Rewind, and Stop.
Note: You should avoid certain miniaturized tape equipment intended
for dictating applications where the microphone and speaker are enclosed
within the unit and no connections are provided to external jacks. If
such equipment is used, you will have to make internal modifications to
reach the desired connection points.
To connect your tape unit to the KIM-1 module, turn off the power
supplies and remove the connector (A) from the module. Add the wires
shown in the sketch:
(A)
MIC
TAPE
UNIT
EARPHONE
P
"AUDIO DATA OUT (HI)
Audio Tape Unit Connections
FIGURE 2.3
13
Keep the leads as short as possible and avoid running the leads near
sources of electrical interference. The connections shown are for typical,
portable type units. The Audio Data Out (LO) signal has a level of approx-
imately 15 mv. (peak) at pin M. Should you desire to use more expensive
and elaborate audio tape equipment, you may prefer to connect the high
level (1 volt peak) audio signal available at pin P to the "LINE" input
of your equipment.
Return the connector (A) to its correct position on the KIM-1 module
and turn on the power supplies. To verify the operation of your audio
cassette equipment, try the following procedures:
1. Reenter the sample program following the procedures
outlined in the previous section (2.4). Try the
sample problem again to be sure the system is
working correctly.
2. Install a cassette in your tape equipment and REWIND
to the limit position.
3. Define the starting and ending address of the program to
be stored and assign an identification number (ID) to
the program.
Press
Keys
See On Display
Step #
AO
xxxx
XX
1
1
!l o
1 F 1!
1 1
OOFl
XX
2
( OA
loll
o 1
OOFl
00
3
1 AO
OOFl
00
4
1 1
II ^ 1
1 F II
5
17F5
XX
5
OA
1 II
1
17F5
00
6
+
1 o II
o 1
17F6
00
7
1 -
1 1 II
o 1
17F7
10
8
+
1 o II
o 1
17F8
00
9
1 +
1 o II
1
17F9
01
10
AO
J
17F9
01
11
[ 1
1 B 1
loll
o 1
1800
XX
12
You will recall that the program we wish to store on tape was loaded
into locations 0000 to OOOF of the memory. Therefore, we define a start-
ing address for recording as 0000 and store this in locations 17F5 and
17F6 (Steps 4 to 7) . We define an ending address for recording as one
more than the last step of our program and stored the value 0010
(= OOOF + 1) in locations 17F7 and 17F8 (Steps 8,9). Finally we pick
an arbitrary ID as 01 and store this value at location 17F9 (Step 10).
Note that before we use the audio cassette unit for recording
or playing back, we must put 00 in location OOFl (Steps 1,2 and 3).
14
The starting address of the tape recording program is 1800. In Steps
11 and 12 we set this address value into the system. If we were to press
the system would proceed to load data on to the magnetic tape. But
first, we'd better start the tapel
4. Select the Record/Play mode of the tape recorder. Wait a
few seconds for the tape to start moving and now:
Press
GO
5 . The display will go dark for a short time and then will
relight showing:
0000 XX
6. As soon as the display relights, the recording is finished
and you should STOP the tape recorder.
Now, you should verify that the recording has taken place correctly
This can be proven by reading the tape you have just recorded. Proceed
as follows :
1. Rewind the tape cassette to its starting position.
2. Turn off the system power supplies and then later,
turn them back on.
This has the effect of destroying your previously stored program
which you already have recorded on tape.
3. Prepare the system for reading the tape as follows:
Press Keys See On Display Step //
RS
AD
DA I
AD I
I AD
GO
lie:
1
O
XXXX XX
OOFl XX
OOFl 00
OOFl 00
17F9 XX
17F9 XX
17F9 01
17F9 01
1873 XX
(Dark)
1
2
3
4
5
6
7
8
9
10
15
The KIM-1 system is now looking for tape input data with the ID
label 01. Recall that this is the same ID label we assigned when we
recorded the program.
4. If your tape unit has a volume control, set the control
at approximately the half way point.
5. If your tape unit has a tone control, set the control
for maximum treble.
6. Now, turn on the tape using the PLAY mode. The tape
will move forward and the system will accept the recorded
data. As soon as the data record (ID=01) has been read,
the display should relight showing:
0000 XX
You may now stop the tape unit. If the display relights and shows;
FFFF XX
this means that the selected record has been located and read but that an
error has occurred during the reading of the data. In this case, press
the key and repeat the read tape procedures from the beginning. If
the FFFF still shows on the display, repeat the entire recording and play-
back procedures checking each step carefully. If the problem persists,
refer to Appendix C, (In Case of Trouble).
If the tape continues to run and the display does not relight, this
means that the system has been unsuccessful in reading any data back from
the tape. In this case, repeat the entire recording and playback proce-
dures checking each step carefully. If the problem persists, refer to
Appendix C, (In Case of Trouble).
7. Assuming that you have read the tape successfully, you
now may verify that the program has been restored to
memory by trying a sample problem. (02 + 03 = 05)
NOTE: The KIM-1 interface circuits for the audio tape system
are designed so that you d^ not require special test
equipment to set up correct operating levels. If you
have followed the procedures indicated, the tape system
should work without the need of any adjustments by you.
16
2.6 ADDING A TELEPRINTER
If you have access to a serial teleprinter, you may add such a unit
to the KIM-1 system with very little effort. One of the more commonly
available units of this type is the Teletype Model 33ASR which we will
use for the purposes of illustration in this section. However, if you
have available different equipment, you may use the information presented
here as a guide to connecting your specific unit. In any case, we recom-
mend you follow the directions offered by the equipment manufacturer in
his instruction manual to effect the desired wiring and connection options.
The KIM-1 provides for a 4 wire interface to the TTY. Specifically,
the "20 MA loop" configuration should be used and you should check that
your TTY has been wired for this configuration. If not, you may easily
change from "60 MA loop" to "20 MA loop" configurations following the
manufacturers directions. The KIM-1 has been designed to work properly
only with a teleprinter operating in full duplex mode. Check the
literature supplied with your teleprinter if you are unsure if your
unit is properly configured. You are not restricted to units with specific
bit rates (10 CPS for TTY) since the KIM-1 system automatically adjusts
for a wide variety of data rates (lOCPS, 15CPS, 30CPS, etc.).
To connect the TTY to the system, proceed as follows:
1. Turn off system power and remove connector (A) from
the module.
2. Add the wires shown in the sketch to connector (A) and
to the appropriate connector on the TTY unit.
17
+ 5V.
O
(A)
I50n
i5on
I — yv\A-
TS J2
^ PRINTER RETURN
U
PRINTER
R KEYBOARD RETURN
MA^
20 MA
^ KEYBOARD
-•
8
7
6
7
1 1
-•
5
TTY ASR 33
r 1
1 1 1
\
4
6
-•
i f i
1 1
TS
J2
RCK
ONE
EXTERNAL SWITCH TO SELECT
EITHER MODE
"-JUMPER FOR TTY OPERATION
TTY Connections
FIGURE 2.4
The jumper wire from A-21 to A-V is used to define for the
KIM-1 system that a teleprinter will be used as the only
input/display device for the system. If you expect to use
both TTY and the KIM-1 keyboard/display, you should install
the switch shown instead of the jumper. Now, the switch,
when open, will allow use of the keyboard and display on
the KIM-1 module and, when closed, will select the tele-
printer as the input/display device. (Of course, you may
use a clip-lead instead of the switch if you desire).
Be sure pins A-21 and A-V are connected. Reinstall con-
nector (A) and return power to the system. Turn-on the TTY.
Press the | Rs | key on the KIM-1 module then press
/rub\
the^UT/ key on the TTY. This step is most important
since the KIM-1 system adjusts automatically to the
bit rate of the serial teleprinter and requires this
first key depression to establish this rate.
18
If everything is working properly you should immediately observe a
message being typed as follows:
KIM
This is a prompting message telling you that the TTY is on-line and the
KIM-1 system is ready to accept commands from the TTY keyboard.
Should the prompting message not be typed press the I I key on the
KIM-1 keyboard and then the (o^ key on the TTY. If the "KIM" message
still is not typed, recheck all connections and the TTY itself and try
again. If the problem persists, refer to Appendix C, (In Case of Trouble)
6. Assuming that the TTY is operable, you may now try a simple
group of operations to verify correct system operation;
Press Keys
@®®®
[sp ace!
©®0
®©®
©
See Printed
KIM
XXXX XX
0002
0002 XX
18.
0003 XX
0004 XX
0003 A5
KIM
XXXX XX
A5.
Step //
Step 1 shows the "KIM" prompting message. In Step 2, an address
(0002) is selected followed by a space key in Step 3. The address cell
0002 together with the data stored at that location (xx) is printed.
Step 4 shows the "modify cell" operation using the (5) key and the hex
data keys preceding. Step 5 shows the incrementing to the next address
cell (0003) after the key. Note that the modification of cell 0002
also occurs. Steps 6 and 7 show the modification of data in cell 0003
and the incrementing to cell 0004. Step 8 shows the action of the key
in backing up one cell to 0003 where we can see from the printout that
the correct data (A5) has been stored at that location. Step 9 shows the
reaction to the key in resetting the system and producing a new "KIM"
prompting message. Note, by the way, that in this example you have
repeated a portion of the program entry exactly as you did in Section 2.4
but this time using the TTY.
19
So much for nowl If all of the operations have occurred properly,
you may be certain that your TTY and KIM-1 module are working together
correctly. We will describe in detail all of the other operations pos-
sible with the TTY in a later section of the manual.
If you have reached this point without problems, you now have
completed all of the required system tests and may be confident that
the KIM-1 module and your peripheral units are all working correctly.
Our next task is to learn more about the KIM-1 system and its operating
programs .
20
CHAPTER 3
THE KIM- 1 SYSTEM
Up to this point you have been engaged in bringing up your KIM-1
system and verifying its correct operation. Now it's time to learn more
about the various parts of the KIM-1, how the parts work together as a
system, and how the operating programs control the various activities of
the system. The diagrams included in this section together with your
full sized system schematic will be helpful in understanding the elements
of your KIM-1 module,
3. 1 KIM-1 SYSTEM DESCRIPTION
Figure 3-1 shows a complete block diagram of the KIM-1 system. You
should note first the presence of the MCS 6502 Microprocessor Array which
acts as the central control element for the system. This unit is an 8
bit microprocessor which communicates with other system elements on three
separate buses. First, a 16 bit address bus permits the 6502 to address
directly up to 65,536 memory locations in the system. Next, an 8 bit,
bidirectional data bus carries data from the 6502 array to any memory
location or from any memory location back to the 6502 array. Lastly, a
control bus carries various timing and control signals between the 6502
array and other system elements.
21
Associated with the 6502 array is a 1 MHz crystal which operates with
an oscillator circuit contained on the 6502 array. This crystal control-
led oscillator is the basic timing source from which all other system
timing signals are derived. In particular, the 02 signal generated by
the 6502 array and used either alone, or gated with other control signals,
is used as the system time base by all other system elements.
The 6502 microprocessor is structured to work in conjunction with
various types of memory. In the KIM-1 system, all memory may be consid-
ered to be of the Read-only (ROM) or Read/Write (RAM) variety. The ROM
portion of the memory provides permanent storage for the operating progams
essential to the control of the KIM-1 system. You will note the inclusion
of two devices, labelled 6530-002 and 6530-003. Each of these devices
include a 1024 byte (8 bits per byte) ROM with different portions of the
operating program stored permanently in each ROM.
RAM type memory is available at three locations in the system.
Again, each of the 6530 arrays include 64 bytes of RAM primarily used for
temporary data storage in support of the operating program. In addition,
a separate 1024 byte RAM is included in the KIM-1 system and provides
memory storage for user defined application programs and data.
Input/output controls for the system also are included within the
6530 arrays. Each 6530 array provides 15 I/O pins with the microprocessor
and operating program defining whether each pin is an input pin or output
pin, what data is to appear on the output pins, and reading the data appear-
ing on input pins. The I/O pins provided on the 6530-002 are dedicated to
interfacing with specific elements of the KIM-1 system including the key-
board, display, TTY interface circuit, and audio tape interface circuit.
The 15 I/O pins on the 6530-003 are brought to a connector and are avail-
able for the user to control a specific application.
22
Finally, each 6530 array includes an interval timer capable of count-
ing a specific number of system clocks to generate precise timing gates.
The exact time interval is preset under program control. The interval
timer on the 6530-003 array is available for a user defined application
program and is not required by the operating programs.
Figure 3-1 shows a major block labelled Control Logic. Included
under this category are an address decoder used for generation of chip
select signals for the 6530 arrays and the static RAM. Also included is
the logic required to debounce the keys for system reset (RS key) and pro-
gram stop (ST key) . Lastly, special logic is included to allow operation
of the system in a "single instruction" mode to facilitate program de-
bugging.
Figure 3-1 shows the keyboard/display logic interfacing with the I/O
pins of the 6530-002. Also shown are the interface circuits for trans-
mission of data to and reception of data from the TTY and audio tape units.
Figure 3-2 shows the detailed interconnections between the MCS 6502
and the two MCS 6530 arrays.
Figure 3-3 shows detailed logic and schematics for the control logic.
Figure 3-4 shows a detailed schematic of the static RAM.
Figure 3-5 and 3-6 show the detailed schematic of the keyboard and
display logic and circuits.
Figure 3-7 details the schematic of the TTY interface circuits.
Figure 3-8 details the schematic of the audio tape cassette interface
circuits .
Figures 3-9 and 3-10 provide a summary of all signals available on
either the Application connector or the Expansion Connector.
The fold-out system schematic shows all of the elements of the system
connected together and all signals appearing on the module connectors.
You may refer to the Hardware Manual included with your KIM-1 module
for additional details on the operating characteristics of the 6502 and
6530 arrays as well as detailed information on system timing.
23
6502
MPU
CONTROL
LOGIC
7T
TV
CD
<
CO
<
CD
C/)
LU
CC
Q
Q
<
V V
6530-002
c
6530-003
c
EXPANSION CONNECTOR
KEYBOARD
AND
DISPLAY
REMOTE
KEYBOARD
TTY
INTERFACE
TTY KYBD
TTY KYBD RTN
TTY PTR
TTY PTR RTN
Lb
AUDIO TAPE
INTERFACE
AUDIO OUT (HI)
AUDIO OUT(LO)
AUDIO IN
APPLICATION I/O BUS (15 I/O LINES) ^
O
I-
o
Ul
2
Z
o
o
<;
o
J
a.
a.
<
I K • 8 RAM
MEMORY
KIM-I Block Diagram
FIGURE 3.1
24
Ul
MPS 6502
O — ; (M ro
CQ £ [Q £ (Q
[& S ffi IS
<<<t<<oooooooQa
I
IRQ
NMI
SYNC
R/W
XTAL
2
LOGIC
cr
>- * 5
i/> (M "V < s in ^.
cr S a: ij: i: it ^
K6
K5
A80
AB I
asz
483
A84
ASS
AB6
AB7
AB8
ABS
RST
080
□ Bl
082
063
□ 84
DBS
□ 86
D87
92
R/W
PA I
PAZ
PA3
PA4
PAS
PAe
PBI
PB2
PBS
PB4
U2
MPS
6530-002
P85
P87
PBO
PA7
O
VCC
K5
RS
ABO
ABI
AB2
PAO
A83
PA 1
AB4
PAZ
AB5
PA3
AB6
PA 4
AB7
PAS
ABB
PA6
AB9
PA 7
OBO
PBO
DBI
PBI
OBZ
Pes
DB3
PB3
DBI
PB4
DBS
PBS
□Be
087
R5T
02
U3
MPS
6530
P87
-003
R/W
40
39
36
35
34
25
40
39
38
37
36
35
24
23
22
21
A- 14
A- 4
A- 3
A-2
A-5
A-6
A-7
A-8
A- 9
A-IO
A-l I
A-(2
A-13
A-16
IL
KEYBOARD
a
DISPLAY
19
17
25
34
TAPE a
TELETYPE
q:
O
H
u
UJ
z
o
z
o
I-
<
u
-I
a
<
HAM
RAM
- R/W
R/W
!2 ^ r 2 «
Ul Ul U UJ UJ
EXPANSION CONNECTOR
Detailed Block Diagram
FIGURE 3.2
25
SYNC
RDY
RST
Q.
CM
o
ID
ABIO
ABI I
ABI2
(PIN 3 ) (0 I
(PIN 37)XTAL
02
R/W
R3
VCC
Rl
MAAr
VCC
SST- SLIDE SWITCH
LOCATED ON KEYBOARD
CLOSED - SST
-V\Ar-o
VCC
14
R 4
10
U 25
D556
C2
U26
R7
.RI2
FROM U2
PIN 4
RS
X
R24
■AAAr
13
12
C3
R25
.RI3
R53
nAVS
CR8
n « ►! O
XI _f-CI8
X
U 16
U I 6
UI6
UI5
V
10
12
I
VCC
ST, RS KEYS LOCATED
ON KEYBOARD
12
13
14
15
D C B A
U4 74LSI45
07 06 05 04 03 2 01 00
16
-OVCC
"1
VCC
R36 O
R37
R38
R35
MAA^
— *<\j<onC: > 5 tu
I I I t I I > I I
UJUJliJUiUJliJ UJ UJ liJ
I I
to s:
UJ Ui
EXPANSION CONNECTOR
V
^ -n XIlUJOUcO
I f I I I I I I
< < <<<<<<
APPLICATION CONNECTOR
CONTROL BUS
Control and Timing
FIGURE 3.3
26
vcc
R39
D OUT
U — 5
(6102)
D IN
U-6
(6102)
U-7
(6102)
U-8
(6102)
U-9
(6102)
U-IO
(6102)
U-ll
(6102)
U-12
(6102)
12 9
12 5
12 2
12 12
II
1 1
12 5
<<<<<<<<< <
n (c _
10 n
1! I
<<<<<<<<<<
1
a — CM lo^owr-
<
IK
ADDRESS BUS
DATA BUS
CONTROL BUS
lKx8 RAM Memory
FIGURE 3.4
27
PBI
15
PB2
14
13
PB3
la
PB4
A
B
U24 ( 74145)
C
ro CM — O
O O O O
T
o
o o
O
(S
O
o
4 3 21 I
>R 41 P R 42 > R 43
' R 44
10
' R45
VCC
II 16 e
^46
R
18
R
19
R
20
02 y —
^ — •
14
R
2 I
# — "
R
22
14
R
23
10
U 18 U \9 U 20 U 2 I
SG
SF
SE
SC
1 — '
>— (
1
1
• — <
1
|3
14
9
3
14
9
U22 U23
|SB ISA
R32 'C^R3I <.R30 <R29 <R28 <R27 <'r26
^
AAA
O
X:
-1
©
A A A
COL F IN
COL E IN
COL IN
COL C IN
C OL A IN
A- X -B
A- W
A-ie
A-20
A-22
A- Y
A-19
A-21
A- V
Keyboard and Display
FIGURE 3.5
28
(6) (8)
ST RS
(12) (2) (4) (9) (14) (3) (5)
PA6 PAS PA4 PA3 PA2 PAI PA0
DA
I
GO^
pc/
1
o
2 4
O 3 O
O
6 8 10
5 O 7 O 9 O 1 1
O O
12 14
O 13 O 15
O O
GO
ST
RS
SST
AD
DA
PC
+
C
D
E
F
8
9
A
B
4
5
6
7
1
2
3
.Aon
SST \^
■RO (I)
•Rl (15)
■R2 (13)
VCC (7)
33GG (10)
•25TT (II)
Keyboard Detail
FIGURE 3.6
29
CONT
TTY AND TAPE
I/O CONTROL
UI6
CM
O
O
6
n
LO
CO
m
<
a:
UJ
I
Gl
a:
UJ
CL
PBS
PA7
PB0
—
-a UI5
V hi
I0|
~9
vcc
o
A-A
TTY KYBO
RTRN {+)
R49
A-R
RETURN
PATH
'7 p
lCR7
|6.2 V
■R48
o
»-
o
UJ
z
z
o
o
TTY PTR
RTRN (+)
A-S
TTY KYBO
1 — 1
> z'
^R47
C5
CR5
1 1
' » ^ , . - ,
» (
<
o
A-T □
a.
a.
<
A- I
^R6
TTY PTR
A-U
TTY Interface
FIGURE 3. 7
30
vcc
Q
m
<
(t PB7
J CONT
E
UJ
a.
.R40
10
m •■
~^^^^y—i — ie^wv-r^\AAr-Hvw— 1
' C4 R6 R34 R33 -±r
U26
12
C4 R6
RI6
-V^/^ OVCC
R33 -±r
AUDIO OUT (LP)
AUDIO OUT (HI)
T T T T T — T r—
Cll CIO C9 CI2 C8 I
Z^: ;i; ?k JS^ 3^cr4
Rl I RIO R9
AUDIO
A-M
O
A-P >-
o
UJ
2
Z
o
o
A-N
g
<
Audio Tape Interface
FIGURE 3.8
31
22
KB Col D
KB Row 1
21
KB Col A
Y
KB Col C
20
KB Col E
X
KB Row 2
19
KB Col B
W
KB Col G
18
KB Col F
V
KB Row 3
17
KB Row
u
TTY PTR
16
PB5
T
TTY KYBD
15
PB7
S
TTY PTR RTRN(+)
14
PA0
R
TTY KYBD RTRN(+)
13
PB4
P
AUDIO OUT HI
12
PB3
N
+12v
11
PB2
M
AUDIO OUT LO
10
PBl
L
AUDIO IN
9
PB0
K
DECODE ENAB
8
PA7
J
K7
7
PA6
H
K5
6
PAS
F
K4
5
PA4
E
K3
4
PAl
D
K2
3
PA2
C
Kl
2
PA3
B
K0
1
VSS GND
A
VCC +5v
Application Connector
FIGURE 3.9
32
22
VSS fiND
g
ram/r/w
21
Y
20
Y
PLL TF<iT
XJ
Iv/ W
V
V
rs./ vv
TT
u
16
T
ART S
15
DB0
s
AB14
14
DBl
ART 3
-L-J
j^ij ^
p
12
DB3
N
ABll
11
DB4
M
ABIO
10
DBS
L
AB9
9
DB6
K
AB8
8
DB7
J
AB7
7
RST
H
AB6
6
NMI
F
AB5
5
RO
E
AB4
4
IRQ
D
AB3
3
01
C
AB2
2
RDY
B
ABl
1
SYNC
A
AB0
Expansion Connector
FIGURE 3.10
33
3.2 KIM- 1 MEMORY ALLOCATION
It has been stated that the 6502 microprocessor array included in
the KIM-1 system is capable of addressing any of 65,536 memory locations.
Obviously, we have not included that much memory in your KIM-1 system and
this section is intended to detail for you exactly what memory locations
are included in the system and where they are located (their exact
addresses) .
Each byte of memory in the system is understood to include 8 bits.
Also, you should note that any addressable location in the system may be
performing any one of four functions:
1. A ROM byte - read-only memory in which we have stored the
operating program.
2. A RAM byte - read/write memory for storage of variable data.
3. An I/O location - these locations include both direction
registers which define the I/O pins to be either input pins
or output pins, and the actual data buffer locations contain-
ing the data to be transmitted on output pins or the data
read from input pins. Any I/O location may be viewed as a
read/write memory location with a specific address.
4. An Interval Timer location - a series of addresses are
reserved for each interval timer in the system. Again, you
may write to the timer to define its counting period or read
from the timer to determine its exact state.
Figure 3-11 shows a block diagram detailing all memory blocks in the
KIM-1 system. Figure 3-12 provides a memory map showing all addressable
locations included in the system and their relationship to each other.
Note also the areas in the memory map indicated as available for expansion
(Section 6 of the manual provides more detail on the subject of memory
expansion). Finally, Figure 3-13 provides a complete listing of all impor
tant memory locations and will be referenced frequently by you when writin
your application programs.
34
Referring to Figure 3-12, note that the memory map shows a block of
8192 address locations all existing in the lowest address space within
the possible 65,536 address locations. This address space is further
divided into eight blocks of 1024 locations each. Each 1024 block is
further divided into four pages of 256 locations each. The "K"
reference defines a specific block of 1024 locations and refers to the
"K" number of the address decoder included within the system control
logic. The "page" reference defines a specific group of 256 addresses.
A total of 32 pages (0 to 31) are included in the 8192 address locations.
The hex codes for certain addresses are shown at strategic locations in
the memory map.
Beginning from the highest address location of the 8192, note that
the first 1024 block (K7) is assigned to the ROM of the 6530-002 and the
second 1024 block (K6) is assigned to the ROM of the 6530-003. The entire
operating program of the KIM-1 system is included in these two blocks.
Next in order, a portion of the K5 block is dedicated to the RAM,
I/O, and Timer locations of the two 6530 arrays. An expanded view of
this address space is shown in Figure 3-12. Note that the RAM addresses
for the 6530-002 (Hex 17EC to 17FF) are reserved for use by the operating
program and should not appear in a user generated application program.
The same is true for the I/O and Timer locations of the 6530-002 which
also are reserved for use by the operating programs.
The next four blocks in order (K4, K3, K2 , Kl) are reserved for
additional memory in an expanded system. In Section 6, the methods for
adding memory will be discussed.
Finally, the lowest 1024 address locations (KO) are assigned to the
static RAM included within the KIM-1 system. You should note that within
this block. Page and Page 1 have special significance. Page 1 is used
as the system stack onto which return addresses and machine status words
are pushed as the system responds to interrupts and subroutine commands.
Page has significance for certain of the special addressing modes avail-
able when programming for the 6502 microprocessor array.
35
Figure 3-12 shows an expanded view of Page and Page 1. Note that
17 addresses (OOEF to OOFF) are reserved for use by the operating program
and must never appear in the user generated application program. Also,
note the comment that a maximum of eight locations may be required on the
stack (Page 1) to service operating program interrupts.
In summary, the user generated application program may make use of
the following areas of memory:
1. All of Page except OOEF to OOFF
2. All of Page 1 (remember that the stack will extend an
extra 8 bytes deep to accommodate the operating program) .
3. All of Page 2 and Page 3.
4. In Page 23:
- All I/O locations from 1700 to 173F
- All 64 bytes of RAM from 1780 to 17BF
- An additional 44 bytes of RAM from 17C0 to 17EB
36
UJ
7T
m
<
I
m
<
en
m
en
<n
UJ
q:
Q
o
<
2 m
IT
ro O O
O K- O
ID OC
UJ
5 1
M h-
to
o
(0 q:
ut
H K
U.
o
UJ
>
CD
<
OC
u.
OD
O
GO
(0
UJ
>-
CD
<
u.
u.
O
2
^ UJ ^
CM K 2
o >- o
-ma:
u.
u.
CD
O
o
UJ
2
o > o
r OD (C
o
o
o
OJ
o
X
CO
ro
O
O
I
o
IC
(0
CVJ
o
o
I
o
lO
to
o
o
6
m
CVJ
O
O
I
o
to
lO
lO
o
o
I
ID
(0
CM
O
o
to
<0
OD
o
<
0§
2
s
>
CM <
S ^ ^
w !r a
(O S <
37
PAGE
3 I
30
29
28
27
26
25
24
23
22
21
20
I 9
I 8
I 7
I 6
I 5
I 4
I 3
12
I I
10
9
8
7
6
5
4
3
2
T
AVAILABLE
FOR
EXPANSION
KIM
ROM
6530-002
KIM
ROM
6530-003
STACK
PAGE
FFFF
2000
IFFF
ICOO
IBFF
HEX
/
1800 /
I7FF
\mL.
64 BYTE
RAM
6530-002
1400
I3FF n
DECODED
FOR 4K
EXPANSION
0400
64 BYTE
RAM
6530-003
I/O a
TIMER
6530-002
I/O a
TIMER
6530-003
03FF / y
OIFF
0000
PAGE
I7FF
I7E7
1740
I73F
1700
IM RAM
I7E6 I
I7C0
iTbF^ I APPLICATION
1780 J
177 F
RAM
•KIM I/O
I APPLICATION
I/O
OIFF
*1
STACK
POINTER
INITIALIZED
OOFF
OOEF
OOEE
17 BYTES
RESERVED
FOR KIM
Memory Map
FIGURE 3.12
38
ADDRESS
AREA
LABEL
FUNCTION
OOEF
OOFO
OOFl
00F2
0OF3
00F4
OOFS
I
Machine
Register
Storage
Buffer
1
PCL
PCH
P
SP
A
Y
X
Program Counter - Low Order Byte
Program Counter - High Order Byte
Status Register
Stack Pointer
Accumulator
Y-Index Register
X-Index Register
1700
1701
1702
1703
t
Application
I/O
i
PAD
PADD
PBD
PBDD
6530-003 A Data Register
6530-003 A Data Direction Register
6530-003 B Data Register
6530-003 B Data Direction Register
1704
i
170F
t
Interval Timer
i
6530-003 Interval Timer
(See Section 1.6 of
Hardware Manual)
17F5
17F6
17F7
17F8
17F9
t
Audio Tape
Load £c Dump
1
SAL
SAH
EAL
EAH
ID
Starting Address - Low Order Byte
Starting Address - High Order Byte
Ending Address - Low Order Byte
Ending Address - High Order Byte
File Identification Number
17FA
17FB
17FC
17FD
17FE
17FF
Interrupt
Vectors
1
NMIL
NMIH
RSTL
RSTH
IRQL
IRQH
NMI Vector
NMI Vector
RST Vector
RST Vector
IRQ Vector
IRQ Vector
Low Order Byte
High Order Byte
Low Order Byte
High Order Byte
Low Order Byte
High Order Byte
1800
1873
Audio Tape
DIIMPT
LOADT
Start Address - Audio Tape Dump
Start Address - Audio Tape Load
ICOO
STOP K^y + SST
Start Address for NMI using KIM
"Save Machine" Routine (Load in
17FA & 17FB)
17F7
17F8
Paper Tape
Dum^ (Q)
EAL
EAH
Ending Address - Low Order Byte
Ending Address - High Order Byte
Special Memory Addresses
FIGURE 3.13
39
3. 3 KIM-1 OPERA TING PR OGRAMS
Figure 3-14 shows a simplified flow chart of the KIM-1 operating
programs. This section provides a brief explanation of these programs
to assist you in understanding the various operating modes of the
system.
First, you should note that when power is first applied to your
automatically is assumed by the operating program. This is true, as well,
for any succeeding depression of the reset key.
For each depression of the reset key, the system is initialized.
At this time, stack pointer values are set, the I/O configuration is
established, and essential status flags are conditioned. Next the
program determines whether the system is to respond to TTY inputs or
is to operate with the keyboard and display on the KIM-1 module.
If the TTY mode has been selected, the program halts and awaits a
first key depression from the TTY (the RubOut Key) . Upon receipt of this
key depression, the program automatically performs a bit rate measurement
and stores the correct value for use in receiving and decoding succeeding
data transfers from the TTY. Note that this bit rate measurement is per-
formed after each depression of the reset key.
The program will proceed immediately to a routine causing the
prompting message ("KIM") to be typed on the TTY. Now, the program halts
at the loop called "Get Character". As each key is depressed on the TTY,
the coded data is accepted and analyzed in the routine called "Execute Key".
The various keys depressed will cause the program to branch to the appro-
priate subroutines required to perform the desired operation. Upon com-
pletion of the individual key executions, the program returns to the "Get
Key" loop and awaits the next key depression.
KIM-1 module and the
key is depressed, control of the system
40
NMI (ST)
RST (RS)
SAVE MPU
REGISTERS
1
INITIALIZE
KB
RO
TTY
BIT RATE
MEASUREMENT
-t — » < START >
PRINT
KIM
GET
CHARACTER
PROCESS
G/RUN KEYS
T
EXIT
KB
TTY
DISPLAY
CELL
NO KEY
DISPLAY
CELL
NO KEY
.AK>
GET
KEY
RUN
EXECUTE
KEY
DISPLAY
CELL
NO KEY
Flow Chart
FIGURE 3.14
IRQ
V
USER OPTION
1873 HEX
AUDIO
- TAPE
LOAD
MEM
FROM
TAPE
1800 HEX
AUDIO
-TAPE
DUMP
MEM
TO TAPE
•4
HEX (0-F)
GO
PC
AD
DA
+
41
Exit from the TTY processing loop will occur in response to:
1. A depression of the reset key,
2. A depression of the G key which initiates execution of
the application program, or
3. A change in the mode from TTY to Keyboard/Display.
If, after system reset and initialization, the Keyboard/Display
mode (KB) is determined to be in effect, the program will proceed dir-
ectly to display, and keyboard scan routines. The program will cause the
display scan to occur continuously ("Display Cell") until one of the keys
on the keyboard is depressed (AK?) . Key validation is performed during
an additional scan cycle. If the key is truly depressed (not noise), the
program proceeds to the routine called "Get Key" in which the exact key
depressed is defined. Next, the program moves to the "Execute Key"
routine where branches to appropriate execution routines will be per-
formed. Finally, after key execution, the program returns to the "Display
Cell" routine and waits for the key to be released. When no key is de-
pressed, the program returns to the normal "Display Cell" routine and
awaits the next key depression.
In either the TTY or KB modes, the audio tape load or dump routines
may be executed using appropriate commands from the selected keyboards.
In either case, completion of the tape load or dump routine allows the
program to return to the "Start" position which will, as usual, activate
the KIM-1 display or cause the "KIM" prompting message on the TTY.
You should note the use of the Stop key to activate the non-maskable
interrupt input (NMI) of the 6502 microprocessor array. Depression of
this key causes an unconditional termination of program execution, a
saving of machine status registers on the stack, and a return to the
control of the operating program.
A second interrupt input is available and referred to as IRQ. This
interrupt may be defined by the user and will cause the program to jump to
any location defined by the user in his program.
42
CHAPTER 4
OPERATING THE KIM-1 SYSTEM
Now that you have a better idea of what is included in your KIM-1
system and haw it operates, its time to provide you with detailed pro-
cedures for all of the operations you can perform with the system. We
will separate our operating procedures into three areas giving specific
direction for the use of the KIM-1 keyboard and display, the audio tape
recorder, and the serial teleprinter (TTY) .
4. 1 USING THE KIM- 1 KE YBOARD AND DISPLA Y
A brief study of your keyboard shows a total of 23 keys and one
slide switch. First, let's list the purpose of each key:
S -
DA I
s -
Sixteen keys used to define the hex code
of address or data
selects the address entry mode
selects the data entry mode
increments the address by +1 but does
not change the entry mode
recalls the address stored in the Program
Counter locations (PCH, PCL) to the display
causes a total system reset and a return to
the control of the operating program
causes program execution to begin starting
at the address shown on the display
terminates the execution of a program and
causes a return to the control of the
operating program
43
You have seen in an earlier chapter that the six digit display in-
cludes a four digit display of an address (left four digits) and a two
digit display of data (right two digits).
Using only the KIM-1 keyboard and display, you may perform any of
the following operations:
1. Select an Address
Press AD followed by any four of the hex entry keys.
The address selected will appear on the display. If an
entry error is made, just continue to enter the correct
hex keys until the desired address shows on the display.
Regardless of what address is selected, the data field of
the display will show the data stored at that address.
2. Modify Data
After selecting the proper address, press [ da| followed by
two hex entry keys which correctly define the data to be
stored at the selected address. The data entered will
appear in the data field of the display to indicate that
the desired code has already been entered.
Note that it is possible for you to-select an address of
a ROM memory cell or even the address of a memory cell that
does not exist in your system. In these cases, you will not
be able to change the data display since it is clearly not
possible for the system to write data to a ROM cell or a
non-existent memory location.
3 . Increment the Address
By pressing the I * I key the address displayed is auto-
matically increased by +1. Of course, the data stored at
the new address will appear on the display. This operation
is useful when a number of successive address l ocat ions must
be read or modified. Note that the use of the | + | key will
not change the entry mode. If you had previously pressed
the AD key, you remain in the address entry mode and a
previous depression of the | da| means you remain in the
data entry mode.
44
4. Recall Program Counter
Whenever the NMI Interrupt pin of the 6502 microprocessor
array is activated, the program execution in progress will
halt and the internal registers of the 6502 are saved in
special memory locations before the control of the system
is r etur ned to the operating program. In the KIM-1 system,
the NMI interrupt may occur in response to a depression of
the I ST I key (stop) or, when operating in the Single Step
mode, after each program instruction is executed following
the depression of the
GO
key.
The I PC I key allows you automatically to recall the value
of the Program Counter at the time an interrupt occurred.
You may have performed a variety of operations since the
interrupt such as inspecting the contents of various
machine registers stored at specific memory locations.
However, when you press the | pc | key, the contents of the
Program Counter at the time ot the interrupt are recalled
to the address field of the display. You now may continue
program execution from that point by pressing the go key.
5 . Execute a Program
Select the sta rting address of the desired program. Now,
press the |go | key and program execution will commence
starting with the address appearing on the display.
6 . Terminate a Program
The I ST I itey is provided to allow termination of program
exec uti on . As mentioned earlier, the | st | key activates
the NMI interrupt input of the 6502 microprocessor array.
Note : The | st | key will operate correctly only if you
store the correct interrupt vector at locations 17FA and
17FB. For most of your work with the KIM-1 system, you
should store the address ICOO in these locations as follows:
45
Now, when the NMI interrupt occurs, the program will return to
location ICOO and will proceed to save all machine registers before
returning control to the operating program.
You should remember to define the NMI vector each time the power
to the system has been interrupted. A failure of the system to react
to the I ST I key means you have forgotten to define the NMI vector.
7 . Single Step Program Execution
In the process of debugging a new program, you will find
the single step execution mode helpful. To operate in
this mode, move the SST slide switch to the ON position
(to your right). Now, depress the go key for each
desired execution of a program step. The display will
show the address and data for the next instruction to
be executed. Note that in the course of stepping
through a program, certain addresses will appear to
be skipped. A program instruction will occupy one, two,
or three bytes of memory depending upon the type of
instruction. In single instruction mode, all of the
bytes involved in the execution of the Instruction are
accessed and the program will halt only on the first
byte of each successive instruction.
Note : SST mode also makes use of the NMI interrupt of the
6502 microprocessor array. Again, the NMI vector must be
defined as described in (6) above if the SST mode is to
work correctly.
This covers all of the standard operations you may perform from the
KIM-1 keyboard. Using combinations of the operations described, you may
wish to perform certain specialized tasks as follows:
1. Define the IRQ Vector
You will recall that a separate interrupt input labelled
IRQ is available as an input to the 6502 microprocessor
array. If you wish to use this feature, you shou ld e nter
the address to which the program will jump. The IRQ
vector is stored in locations 17FE and 17FF.
2 . Interrogate Machine Status
We have mentioned that after an NMI interrupt in response
to the I ST I key or during the SST mode, the contents of
various machine registers are stored in specific memory
locations. If you wish to inspect these locations, their
addresses are:
46
OOEF
PCL
OOFO
PCH
OOFl
Status Register (P)
00F2
Stack Pointer (SP)
00F3
Accumulator (A)
00F4
Y Index Register
00F5
X Index Register
4.2 USING THE AUDIO TAPE RECORDER
There are two basic operations possible when working with your audio
tape system. You may transfer data from the KIM-1 memory and record it
on tape. Or, you may read back a previously recorded tape, transferring
the data on tape into the KIM-1 memory.
Recording on Audio Tape
The procedure for recording on audio tape requires that you
perform the following steps:
1. Clear decimal mode by entering 00 in location OOFl.
Define an Identification number (ID) for the data
block you are about to record. This two digit number
is loaded into address 17F9. Don't use ID = 00 or
ID = FF.
2. Define the starting address of the data block to be
transferred. This address is to be loaded into
locations :
17F5 = Starting Address Low (SAL)
17F6 = Starting Address High (SAH)
3. Define the ending address as one greater than the
last address in the data block to be recorded. The
ending address is to be loaded into locations :
17F7 = End Address Low (EAL)
17F8 - End Address High (EAH)
As an example, assume you wish to record a data block from
address 0200 up to and including address 03FF. (All of Pages 2 and 3).
You wish to assign an ID number of 05 to this block. Using the KIM-1
keyboard, you should load the data shown into the addresses indicated
so that:
OOFl
17F5
17F6
17F7
17F8
17F9
00 (Clear Decimal Mode)
00 (SAL)
02 (SAH)
00 (EAL)
04 (EAH)
06 (ID)
03FF + 1
47
Note that the ending address must be greater than the starting
address for proper operation.
4. Assuming that you are using a new cassette on which
no data has been stored previously, insert the
cassette in the unit and rewind the tape to its
start position.
5. Select the starting address of the tape record program.
This address is 1800.
6. Select the Play/Record mode of the audio unit and allow
several seconds for the tape to begin to move.
7. Press the | go| key and the recording process will begin.
The display will be blanked for a period and then will
relight showing 0000 xx. This means that the data
block selected has been recorded.
8. You may now stop the tape or allow some additional
seconds of blank tape and then stop the unit.
Loading Data From Audio Tape
The procedure for loading data from an audio tape into the
KIM-1 memory requires that you perform the following steps:
1. Clear decimal mode by entering 00 in location OOFl.
Define the ID number of the data block to be loaded
from tape. The ID number is loaded into address 17F9.
2. Select the starting address of the Tape Load program.
This address is 1873^^^.
3. Press the | go| key. The KIM-1 system is now waiting
for the appearance of data from the tape unit.
4. Load the cassette and, presuming you do not know where
on the tape the data block is recorded, rewind the tape
to its starting position. Check the volume control
setting.
5. Start the audio tape unit in its Play mode and observe
that the tape begins to move.
6. Wait for the KIM-1 display to relight showing 0000 xx.
This means the data block has been loaded successfully
from the tape into the KIM-1 memory. If the display
relights with FFFF xx, the correct data block has been
found but there has been an error detected during the
read operation. If the tape continues to run and the
display never relights, the system has not been
successful in finding the data block with the specific
ID number you requested.
48
7. If in step (1), you had selected an ID = 00, the ID
number recorded on the tape will be ignored and the
system will read the first valid data block encountered
on the tape. The data read from the tape will be
loaded into memory address as specified on the tape.
8. If, in step (1), you had selected an ID = FF, the ID
number recorded on the tape will be ignored and the sys-
tem will read the first valid data block encountered on
the tape. In addition, the data block will be loaded
into successive memory locations beginning at the
address specified in locations 17F5 and 17F6 (SAL, SAH)
instead of the locations specified on the tape.
Special Operations with Audio Tape
The KIM-1 system causes data to be recorded on audio tape with
a specific format as detailed in Appendix E. Each recorded data block is
preceeded by a group of synchronizing characters together with an identi-
fication code to define the specific block. Data blocks may be of arbi-
trary length.
With a little care, there is no reason for you not to include a
number of recorded data blocks on the same tape. If you are recording
blocks in sequence and have not rewound the tape between blocks, you need
only specify the parameters of each new block (ID, SAL, SAH, EAH, EAL) and
proceed with recording the new block.
If the tape has been rewound, you will need to know the ID
number of the last recorded data block. Rewind the tape to its starting
point and set up the parameters required to read the last recorded data
block. After reading this block, stop the tape and you may now proceed
to add a new block or blocks to the tape.
If you wish, you may add voice messages between the recorded
data blocks on the tape. The KIM-1 system will ignore these audio
messages when the tape is read back. Of course, you will need to install
an earphone or speaker in parallel with the KIM-1 audio tape data input
pin in order to hear the voice messages.
We d£ not recommend that you attempt to record data blocks in
areas of the tape which have been used previously for recorded data.
Variations in tape speed and block lengths can result in overlapping of
recorded data which may be read incorrectly by the KIM-1 system.
49
4.3 USING A SERIAL TELEPRINTER
The addition of a serial teleprinter (such as the Teletype Model
33ASR) to work with the KIM-1 system permits a variety of special opera-
tions to be performed. In all cases , you define desired operations by
depressing the proper keys while simultaneously producing a hard -copy
printed record of each operation. If your teleprinter is equipped
with a paper tape reader/punch, you may generate or read paper tapes
using the KIM-1 system. Using the serial teleprinter, you may perform
the following operations:
Select an Address
Type four hex keys (0 to F) to define the desired address.
Next, press the space | bar.
The printer will respond showing the address code selected
followed by a two digit hex code for data stored at the selected
address location:
Type: 1234
SPACE
Printer Responds: 1234 AF
showing that the data AF is stored at location 1234.
Modify Data
Select an address as in the previous section. Now type two hex
characters to define the data to be stored at that address. Next type
the ® key to authorize the modification of data at the selected address:
Type: 1234 I space |
Printer Responds : 1234 AF
Type: 6D
Printer Responds: 1235 B7
Note that the selected address (1234) has been modified and the system
increments automatically to the next address (1235).
Note : Leading zero's need not be entered for either address
or data fields: For example:
EF I SPACE I selects address OOEF
E I SPACE I selects address OOOE
A enters data OA
enters data 00 (etc.)
50
Step to Next Address
Type to step to the next address without modifying the
current address :
See Printed: 1234 AF
Type:
Printer Responds: 1235 B7
Type:
Printer Responds: 1236 C8 (etc.)
Step to Preceeding Address
Type (lf) to step back to the preceeding address:
See Printed: 1234 AF
Type:
Printer Responds: 1233 9D
Type:
Printer Responds
©
1232 8E
(etc. )
message
proceed
Abort Current Operation
Type to terminate
will be printed ("KIM") indicating that a new operation may
Type (ouy) to terminate the current operation. The prompting
Type:
Printer Responds;
Type:
Printer Responds:
1264
KIM
XXXX XX
1234
1234 AF
SPACE
^RUB^
In the example, the [puTj key is used to correct an erroneous
address selection.
fRUBA
Note: The key must be depressed after each depression
of the KIM-1 reset key in order to allow the operating
program to define the serial bit rate for the tele-
printer.
51
Load Paper Tape
Paper Tapes suitable for use with the KIM-1 system are generated
using the format shown in Appendix F. To read such a tape into the KIM-1
system, proceed as follows:
1. Load the punched paper tape on to the tape mechanism
2. Type
3. Activate the paper tape reader
The paper tape will advance and data will be loaded into addresses
as specified on the tape. A printed copy of the data read will be generated
simultaneously with the reading of the paper tape.
Check-sums are generated during the reading of the paper tape
and are compared to check-sums already contained on the tape. A check-
sum error will cause an error message to appear in the printed copy.
Punch Paper Tape
The KIM-1 system can be used to punch paper tapes having the
format described in Appendix F. The procedures for generating these
tapes is as follows:
1. Define the starting address and ending address of the
data block to be punched on the paper tape.
2. Load blank paper tape on the punch unit and activate
the punch.
Type: Q©©Q I space
See Printed: 17F7 xx
Type : ©0©
See Printed: 17F8 xx
Type : ®®®
See Printed: 17F9 xx
Type : ©®®
See Printed: 0200 xx
SPACE
52
You have now loaded the ending address (03FF) Into address
locations 17F7 (EAL) and 17F8 (EAH) . The starting address (0200) Is
selected as shown.
3 • Now type (§)
The paper tape will advance snd punching of the data
will proceed. Simultaneously, a printed record of
the data will be typed.
List Program
A printed record of the contents of the KIM-1 memory may be
typed. The procedure Is the same as for punching paper tape except that
the punch mechanism is not activated.
Execute Program
To initiate execution of a program using the TTY keyboard, the
following procedures should be followed:
1. Enter the starting address of the program
2. Type©
For example, to begin program execution from
address location 0200:
Type: 0®® I space |
See Printed: 0200 xx
Type : ©
Program execution begins from, location 0200 and will
continue until the | st| or Prs] keys of the KIM-1
module are depressed. The single step feature may
be employed while in the TTY mode.
53
CHAPTER 5
LET'S TRY A REAL APPLICATION
It is not practical in this manual to describe every possible
application or progrannning technique. However, now that you have become
familiar with the basic elements and operating procedures of the KIM-1
system, this section will show you how to apply what you have learned in
a simple but realistic application example.
Our example will involve the generation of a variable frequency
square wave which will be connected to a speaker to produce an audible
tone. The frequency of the tone will be selected using a set of seven
toggle switches. We will proceed through the example by defining the in-
terface, writing and entering the program, and executing the program.
Finally, we will study a series of program debugging techniques which
will be useful to you for any new program you ma.y write.
5.7 DEFINING THE INTERFACE
You will recall that a group of 15 I/O pins are brought to the
Application connector from the 6530-003 array. The logic and circuit
details concerning these I/O pins are described in Appendix H and in
Section 1.6 of the Hardware Manual ("Peripheral Interface/Memory
Device MCS 6530").
55
For our application example we will use eight of these I/O pins.
One pin (PA0) will be used as an output line to supply a square wave to
a driver circuit and speaker. The other seven I/O pins (PAl to PA7) are
defined as input points with a SPST toggle switch connected to each.
Figure 5-1 shows the circuit configuration for this example. Note that
the remaining seven I/O pins (the PB port) are not used for this problem.
For the switches connected to the input pins, we would like the sense
of the switch to be defined as a logic "0" when open and a logic "1" when
closed. By connecting the switches to ground, we are producing exactly
the opposite sense and must remember to complement the switch states with
software when we write our program. Also, we must define now that the
switch at PAl is to be the LSB (least significant bit) and the switch at
PA7 is to be the MSB (most significant bit) of the seven bit binary word
formed by all seven switches. In this way, the state of the switches can
define a binary number from zero (all switches open) to 127 (all switches
closed) .
56
A-8 A-7 A-6 A-5 A-2 A-3 A-4 A-14
PA7
PA6
PAS
PA4
PA3
PAZ
PA 1
PA0
1^ 1^ 1^ 1^ 1^ n
APPLICATION
CONNECTOR
-♦PO«T A
3.3K"
+ 5 V.
3.3K:
■27 a
en
SPKR
mi
A-15
A- 16
A-13
A-12
A-ll
A- 10
A- 9
PB7
PBS
PB4
PB3
PB2
PBI
PB0
( THE
B PORT IS
NOT
USED
IN THIS EXAMPLE
CONNECTOR
-♦PORT B
Speaker Application
FIGURE 5.1
57
5. 2 WRITING THE PROGRAM
Having defined the interface for our application, we may proceed now to
write our program. The effort proceeds in four stages:
1. Generate a flow chart
2. Generate assembly language code
3. Analyze the program
4. Generate machine language code
START
FLOW CHART
Initialization
(Define I/O)
i
Toggle PA0
(Speaker Output)
\
Read Seven Switches
& Complement
\
Delay
Delay Defined by
Switch Settings
58
Briefly, our flow chart shows a first step of system initialization.
During this step, we must define the I/O configuration of the system in
that pin PA0 becomes the output to the speaker and that pins PAl to PA7
become inputs from the seven switches.
After initialization, a loop is set up which begins by inverting the
state of PACi (Toggle PA0) . Next, the state of the switches is read and
the data is complemented to produce the correct "sense" from the switches.
The value so read is used to define a delay before returning to the start
of the loop and again toggling the state of PA0. A little thought will
show that this loop will produce a square wave with a frequency determined
by the setting of the seven switches.
Assembly Language Program
Our next task is to convert the simple flow chart into a
program. The program is first written in "Assembly Language". You should
refer to your Programming Manual to become familiar with all of the pos-
sible 6502 instructions (especially see Appendix B; Instruction Summary).
Figure 5-2 shows the application example programmed in assembly language.
59
LABEL
OP CODE
OPERAND
CYCLES
COMMENTS
INIT
LDA
#$01
2
Define I/O 0=lnput l=Output
STA
PADD
4
PADD = PORT A DATA DIRECTION REG.
START
INC
PAD
6
Toggle PA0, PA1-PA7 Inputs
not affected
READ
LDA
PAD
4
READ switches into accumulator
EOR
#$FF
2
Complement switch value
LSR
A
2
Shift Accumulator 1 bit to right
TAX
2
Transfer final count into X-Index
DELAY
DEX
2
Delay by an amount specified
BPL
DELAY
3,2
By the count in the X-Index
BMI
START
3
Go To START
PADD
=$1701
Define absolute address of
Data Direction Reg. A
PAD
=$1700
Define absolute address of
Data Reg. A
Assembly Language Listing
FIGURE 5.2
60
You will note that each line of the program is broken into
several fields:
- A label field permitting you to assign a "name" to
a specific location in the program.
- An Operation Code field (Op Code) in which the exact
instruction to be executed is defined.
- An Operand Field where the exact data required by the
instruction is defined together with certain symbols
defining addressing modes or data formats. Symbols
encountered generally in MOS Technology, Inc. manuals
are:
#
Immediate Addressing
$
Hex Code
@
Octal Code
%
Binary Code
t
ASCII literal
Equates a label to a value
- A Machine Cycle field defining the total number of
machine cycles required to execute an instruction.
(This information is derived from Appendix B of
the Programming Manual) ,
- A Comment Field where the programmer may define the
intent of specific program steps.
Program Analysis
The inclusion of the "machine cycle" information of the program
chart (Figure 5-2) allows us to analyze the exact timing relationships
involved in our program example. Note that the KIM-1 system operates
from a fixed frequency (1 MHz) oscillator with each machine cycle being
lys. Therefore, an instruction like "INC PAD" which requires 6 machine
cycles will be executed in a 6ys period.
61
By counting the total machine cycles occurring between each
toggle of an equation for the square wave frequency can be developed.
The actual frequency is determined by the position of the seven switches,
the number of machine cycles between each toggle of PA0, and the basic
clock rate (1 MHz) of the KIM-1 system. Figure 5-3 shows the waveform
of the PA0 square wave and the derived equations for computing the
exact frequency.
PAe)
T=23+(CNT-5)USEC
T = 2 C23 + (CNT 5)3 USEC
FREQ =
10'
T 46-1-IO-CNT
CPS
note: cnt equals the value in x- index
which was calculated from the
seven switches os cnts 127
Square Wave Output
FIGURE 5.3
62
Machine Language Coding
Our next problem is to convert our assembly language program
into a program written in "machine language". The quickest and most
foolproof method for accomplishing this conversion is by using the
MOS Technology, Inc. Assembler (available for use on the time share
services of United Computing Systems, Inc.). If you choose not to
use this method, you will need to convert your source program to
machine code using "paper-and-pencil" techniques.
You should proceed by constructing a table similar to that
shown in Figure 5-4.
ADDRESS
INSTRUCTION
S01JRCE CODE
BYTE 1
BYTE 2
BYTE 3
LABEL
OP CODE
OPERAND
0200
A9
01
INIT
LDA
#$01
0202
8D
01
17
STA
PADD
0205
EE
00
17
START
INC
PAD
0208
AD
00
17
READ
LDA
PAD
020B
49
FF
EOR
#$FF
020D
4A
LSR
A
020E
AA
TAX
020F
CA
DELAY
DEX
0210
10
FD
BPL
DELAY
0212
30
Fl
BMI
START
0214
Machine Language Code Table
FIGURE 5.4
The source code contained in your assembly language program
(Figure 5-2) is entered into the table first. A column is provided to
allow you to define the specific address at which an instruction is
located. The Instruction column provides space for defining one, two,
or three byte instructions. (Please refer to Appendix B of the Program-
ming Manual or to your Programming Card for specific Op Codes) .
63
As an example, the first source instruction is LDA #$01 which,
when translated, means load the accumulator with the byte stored in the
next program location (hex 01) . This is the "immediate" addressing
mode defined by the "#" symbol. The Op Code for LDA# is A9. This
value is entered in the first column under the heading, Instruction.
The next column contains the hex 01 value defined by the source state-
ment. The initial address for the program is inserted in the "Address"
column as 0200 (an arbitrary selection). The total instruction LDA #$01
now occupies address locations 0200 and 0201.
The next available address is 0202 which is inserted in the
"Address" column for the next source Instruction. In this manner, you
will proceed through all of the source statements decoding each and
entering one, two, or three bytes of machine code as required in the
"Instruction" column. The "Address" column will contain the address of
the first byte of machine code (the Op Code) for each source statement.
In cases where the operand of the source statement is a symbol,
the address to which the symbol has been equated should be filled in as
the proper machine code. For example, the source statement "INC PAD"
requires the incrementing of data stored at a location "PAD" defined in
our assembly programs to have the address: PAD = 1700. Therefore, the
address 1700 is entered as the second and third bytes of the source
statement "INC PAD". (See Figure 5-4). Note also that when entering
an address, such as 1700, the low order byte (00) is entered first and
immediately after the Op Code and the high order byte (17) is entered
next as the third byte of the instruction.
When dealing with branch instructions (BPL, BMI, etc.), you
will need to calculate the exact value of the offset which may be either
positive (branch forward) or negative (branch backward) . You should refer
to Section 4.1.1 of the Programming Manual to explore "Basic Concept of
Relative Branching." As an example, the source statement "BMI START" (See
Figures 5-2 and 5-4) requires a branch backward by (-15) locations to the
address labelled "START" (from address 0213 backward to 0205 inclusive).
64
(The 2's complement of the -15 displacement is Fl which you should
HllA
insert at location 0212) . Had the branch been to a forward location
the positive value of the offset would be inserted rather than the 2's
complement value.
5.3 ENTERING THE PROGRAM
With the program now reduced to machine language code, you may enter
the program address and data codes listed in Figure 5-4 following the
procedures detailed in Section 2.4. The procedure for entering the program
is as follows:
Press Keys S ee On Display
AD 1
1 2 1 1 1 1
0200
XX
1 DA I
1 A M 9 1
0200
A9
1 + 1
1
0201
01
1 +
Is 1 1 D !
0202
8D
+ 1
M 1 1
0203
01
1 + I
1 1 1 1 V 1
0204
17
1 c 1 1 c 1
0205
EE
+
1 rsi
0206
00
+ 1
1 1 M 7 1
0207
17
+ 1
1 A M D 1
0208
AD
+ 1
1 1
0209
00
+ 1
020A
17
1 + 1
1 4 1 1 9 I
020B
49
1 + I
F 1 F 1
020C
FF
+ 1
1 4 1 1 A 1
020D
4A
UJ
020E
AA
1 + '
1 C 1 A 1
020F
CA
+ 1
1 1 I 1 1
0210
10
+ 1
0211
FD
+ 1
1 3
0212
30
1 + 1
F M 1 1
0213
Fl
Key Sequences.
Enter Program
FIGURE 5.5
65
5. 4 EXECUTING THE PR OGRAM
With the program entered, you may proceed to program execution.
First, if the NMI vector has not been defined previously, enter the
vector as follows :
Press Keys See Displayed
AD 1 I 7 I F I A 17FA XX
[da] Qo^ [JJ 17FA 00
LiJ LU LcJ 17FB IC
This procedure insures that the | st [ key will be effective in
terminating the program. Now, select the starting address of your
program (0200) and begin execution as follows:
Press Keys See Displayed
0200 A9
GO (Dark)
The program will now execute. If your seven selector switches all
are open, you will probably hear no sound from the speaker because the
square wave frequency is too high. If all selector switches are closed,
you will hear in the speaker the lowest frequency that can be generated
with the program as currently written. You may experiment with other
combinations of switch settings to hear a variety of tones from the
speaker.
Depression of the | st | key will cause the program execution to stop
(the tone will terminate) and the KIM-1 display will relight. The display
will show the address and data for the next instruction to be executed
(probably 020F or 0210 since this is the delay loop where the program
spends most of its running time) .
66
5.5 PROGRAM DEBUGGING AND MODIFICATION
If your program did not execute correctly, you would follow a
debugging procedure involving the following steps:
Step 1 : List the Program
First make sure you have entered the program steps
correctly. Select the starting address ( |ad | | o | | 2 | | | | | )
and observe that the correct data (A9) is displayed. Now, using
the I + [ key, step through the remaining program locations check-
ing for the correct data stored in each location.
Step 2 : Single Step the Program
Follow the procedures listed in Section 5-4 for program
execution but before depressing the go key, place the SST
slide switch in the ON position. Now, press the go key and
the first instruction will be executed. The display will
relight indicating that the operating program is again in
control of the system. The address displayed will be the
address of the first byte of the next instruction to be
executed. You may press the go key again to execute the
next instruction or you may choose to investigate changes in
the contents of machine registers stored in selected memory
locations (See Figure 3-13) . The procedure detailed in Figure 5-6
gives a good indication of the various operations you may wish
to perform in the SST mode.
Step 3 : Check the I/O Operations
If program entry has been verified and program execution
in the SST mode appears to be normal, you may wish to verify the
correct operation of your specific I/O configuration.
You should recall that writing to or reading from any
I/O port is the same as reading from or writing to any other
memory location in the system. Therefore, if you select the
address of an I/O port, the KIM-1 display will show you the hex
code for the data being read from that address and thus, directly
indicate the state of each I/O pin in the port. For example, the
67
address of the I/O port used for your sample program is 1700.
Press I ad| | 7 | | o | | o | and the display will show the hex
code corresponding to the settings of your selector switches.
If you change the positions of your selector switches, you will
sec the hex code ch^ge In the data field of the display.
Now, leave the same address (1700) selected an<i press
the I DA I key. If you press any of the hex keys [ q [ to [ f [ ,
you will write the data to the I/O port (1700). Since seven
of the pins of this I/O port are defined as inputs, only one
(PA0) will act as an output and will respond to the data
entered by you from the keyboard. Try alternating rapidly
between the | o | and | i | keys and you should hear clicking in
the speaker indicating that you are successfully toggling
the PA0 pin.
This concept of using the KIM-1 keyboard and display
to exercise and verify the operation of I/O ports is a
generally useful technique for debugging the hardware
portions of most specific applications.
68
Press Keys
See Displayed
Comments
m m m
I ssT -8:1 °
Z3 S
0200 A9 Select first instruction address
0200 A9 Set SST to ON; All selector
switches open
0202 8D Accumulator now loaded with $01
0205 EE PADD now loaded
0208 AD PA0 now toggled
020B 49 Switch values (PA1-PA7) now
loaded
020D 4A Accumulator now complemented
020E AA Accumulator now right shifted
1 Bit
00F3 XX Display Accumulator
00F4 XX Display Y - INDEX
OOFS 00 Display X - INDEX
020E AA Restore PC (TAX will
execute next)
020F CA Accumulator now loaded in
X- INDEX
00F3 00 Display Accumulator
00F4 XX Display Y-INDEX
00F5 00 Display X-INDEX (A=O^X)
020F CA Restore PC
0210 10 DEX now completed
OOFS FF Display X-INDEX (X<0)
0210 10 Restore PC
0212 30 No branch (Result of DEX
not positive)
0205 EE Branch (Result of DEX is
negative) .
SST Mode: Sample Operation
FIGURE 5.6
69
CHAPTER 6
EXPANDING YOUR SYSTEM
In earlier sections you have learned that the MCS 6502 Microprocessor
Array is capable of directly addressing up to 65,536 locations (bytes) of
memory. (Usually abbreviated to 65K where "K" for the remainder of this
section is to mean 1024 memory locations). In this section, we will
discuss first the techniques for adding memory or I/O locations to the
system and next, the proper handling of interrupt vectors in an expanded
system.
6. 1 MEMOR YAND IjO EXPANSION
In the KIM-1 system, the management of input/output data is handled
exactly the same as transfers to or from any other memory location in the
system. There are no instructions dealing specifically with input/output
transfers. Instead, transfer of data is accomplished by reading from or
writing to registers connected to the data bus and to I/O pins in specific
I/O interface devices (such as the 6530 array). These registers have a
specific address in the system just as does any other memory location.
Therefore, when we speak of expanding the memory of the KIM-1 system, we
are defining the methods for expanding both the real memory (RAM, ROM,
PROM, etc.) as well as the I/O ports since they are both treated exactly
alike as far as address assignments are concerned.
71
The first and most easilly implemented memory expansion is the
addition of up to 4K of memory space. You will recall that
the lowest 8K memory locations are defined by an address decoder included
on the KIM-1 module, (Device U4 on the schematic). The eight outputs
of this decoder (K0 to K7) each define a IK block of addresses in the
lowest 8K of the memory map. Three" of the outputs (K5 , K6 , K7) are
used to select ROM, RAM, I/O and Timer locations on the two 6530 arrays
while a fourth (K0) is used to select the 1024 locations of the static
RAM memory. The remaining four outputs (Kl, K2, K3, K4) are not used
on the KIM-l module but instead, are brought out to the Expansion connector
for use as chip selects for memory or I/O additions.
Figure 6-1 shows the proper method for deriving the four chip select
signals for the additional 4K of memory. Note that one of input pins of
the decoder (D) was brought out to the Application Connector. It was
this pin which we asked you to connect to ground in Chapter 2 of this
manual. As long as this point remains connected to ground, the decoder
will always select the lowest 8K addresses of the memory field regardless
of the state of AB13, AB14, and AB15 .
If you wish to expand the memory and I/O address space beyond the
lower 8K addresses, you must arrange to de-select the lower 8K memory
block while selecting some other 8K block. One suggested method for
expanding beyond the lower 8K space is shown in Figure 6-2.
Note that the three high order address bits (AB13, AB14, AB15) are
connected to a decoder. The eight outputs of the decoder act to divide
the total 65K memory space into eight blocks of 8K each (8K0, 8K1, etc.).
Now, the 8K0 output may be returned as the fourth input (D) to the de-
coder (U4) on the KIM-1 module causing the proper selection and de-selec-
tion of this block within the total address space. The remaining seven
outputs (8K1 to 8K7) may be used to select and de-select the additional
decoders shown in Figure 6-2. You need add only as many decoders (one
for each 8K block of memory) as you need for your desired memory expansion.
72
A word of caution is in order when you decide to add memory to your
system. You have noticed the inclusion of the line receivers for the
ABIO, ABll, and AB12 signals, (See Figure 6-2). These devices are
included because of loading limitations placed on the address bus lines
of the 6502 array (Each such line is capable of driving one standard
TTL load and 130pf of capacity. See Appendix G) .
VCCO
U4 ^
74LS145 I
2
3
A 4
B 5
C 6
D 7
Kl
K2
K3
K4
K5
K6
K7
I K X 8 RAM ON
KIM -I BOARD
2-6530 DEVICES
ON KIM- 1 BOARD
IHj|h|f|e|d|cTb1-
APPLICATION CONNECTOR
^ K> OJ —
^ ^ ^ ^
AVAILABLE FOR 4K
EXPANSION (PULL-UP REO'O)
4K Expansion
FIGURE 6.1
73
ovcc
4 K MEMORY
OR I/O)
NOTE:
PULL UP RESISTOR IS
REQ'D IF 74145'S
ARE USED.
rv o >.
A
K9
B
1
2
KIO
C
KM
D
3
4
5
6
Ki2 >
KI3
KI4
74145
7
KI5
KI6 ^
1
A
KI7
B
2
KI8
C
3
KI9
D
4
K20 >
5
K2I
6
K22
74145
7
K23
J
8K MEMORY
OR I/O
8K MEMORY
OR I/O
K58 ^
A
K59
B
K60
C
K6I
D
K62
K63
K64
74145
K65
8K
OR
MEMORY
I/O
VECTOR SELECT
(SEE 6.2)
65^" Expansion
FIGURE 6.2
74
Before deciding how to expand your system, we reconimend a careful study
of all of the loading limitations of the KIM-1 signals since almost
certainly you will require additional buffering circuits if correct
operation is to be achieved.
6. 2 INTERR UPT VECTOR MANAGEMENT
We have referred several times in earlier sections to the interrupt
features of the 6502 Microprocessor Array. We suggest now a careful
readin-g of Section 9 of the Programming Manual for the subject "Reset
and Interrupt Considerations".
In summary, there are three possible types of interrupt: Reset, NMI ,
and IRQ. Each will occur in response to an activation of one of the three
pins of the 6502 array (RST, NMI, IRQ). In response to these inputs, the
6502 array will fetch the data stored at a specific pair of addresses and
load the data fetched into the program counter. The addresses are hardware
determined and not under the control of the programmer. The specific
addresses for each type of interrupt are:
FFFA, FFFB - NMI Vector
FFFC, FFFD - RsY Vector
FFFE, FFFF - IRQ Vector
You will note that these addresses define the highest six locations in
the 65K memory map.
In the KIM-1 system, three address bits (AB13, AB14, AB15) are not
decoded at all. Therefore, when the 6502 array generates a fetch from
FFFC and FFFD in response to a RST input, these addresses will be read
as IFFC and IFFD and the reset vector will be fetched from these locations.
You now see that all interrupt vectors will be fetched from the top 6
locations of the lowest 8K block of memory which is the only memory block
decoded for the unexpanded KIM-1 system.
75
It is typical in any system to store the interrupt vectors in ROM
so that they are immediately available after power-on. However, it is
desirable that for the NMI and IRQ interrupts, the programmer be allowed
to define as a variable the exact vector to which these interrupts will
direct the system. Accordingly, the NMI and IRQ vector locations contain
an indirect jump instruction referencing a RAM location into which the
programmer will store the specific vector for the two types of interrupt.
In the KIM-1 system, locations 17FA and 17FB contain the actual NMI vector
and 17FE with 17FF contain the actual IRQ vector. The RST vector is not
handled in this manner and always directs the system to the first step
of the power-on initialization routine.
But what happens if we expand our memory above the lowest 8K block
included in the KIM-1 system? Recall that we now must use AB13, AB14,
and AB15 to decode the additional address locations of the memory. By so
doing, the interrupt vector locations are no longer located in the K7 memory
block since the decoder (U4) is de-selected in response to the addresses
generated by the 6502 array in fetching the interrupt vectors (FFFA for
example) . We would have the same problem even in an unexpanded system
if we wished to use a RST vector and initialization routine different
than what the KIM-1 system provides and if the RST vector was to be
located in a IK block lower than K7 (K0 for instance).
The solution to this dilemma is to generate logically a special
signal for Interrupt select. Referring to Figure 6-2, a special signal
called "Vector Select" is created to define the highest IK memory block
(K65) . The fetch of any interrupt vector V7ill cause this signal to
go low "Select". Assuming that the K65 state is not used to select RAM,
this signal may be "wire-or'd" with any one of the other "K" signals
(K0 to K64) to define exactly which IK block is to contain the interrupt
vectors .
76
As an example, assume that you have connected the K65 "Vector Select"
line to the K0 line. When a RST occurs, the 6502 array generates a fetch
from locations FFFC and FFFD. These addresses cause K65 to be selected
which, in turn, accesses the K0 field of the memory and causes the actual
fetch of the RST vector from locations 03FC and 03FD. (Had you chosen to
connect K65 to K7, the fetch of the reset vectors would occur from
locations IFFC and IFFD) .
In this way, the highest six addresses of any IK block of memory may
be used to supply the interrupt vectors for the system. If desired, a
switch could be installed to allow you to select different areas of memory
as the source locations for the interrupt vectors. (By the way, we
selected the 75145 type decoders in Figure 6-2 specifically to allow the
"wire-or" of K65 with any other K. This is possible because the 75145
decoder is provided with open-collector outputs which allows "wire-or"
of several states using an external load resistor.)
An even simpler arrangement using the "Vector Select" approach is
shown in Figure 6-3. Here, the KIM-1 system is assumed to have only the
lower 8K of memory in place. The address decoder (U4) is de-selected
using the AB15 signal which becomes "true" whenever an interrupt vector
fetch is initiated by the system. The same signal (AB15) is inverted and
"wire-or 'd" through a switch to the K0 or the K7 chip select lines. Now,
depending upon the position of the switch, interrupt vectors will be
fetched from the top 6 addresses of either block K0 or K7. K0 in the
KIM-1 system is the RAM and K7 is the ROM in the 6530-002 array (the
operating program). In this way, you may have two different sets of inter-
rupt vectors in your system and may select which set is to be used with a
simple switch.
77
ABI5
ABIO
ABI I
AS 12
KIM-I
IK
+ 5V -VW — t
U4
74LSI45
A
B
C
D
7405 OR 7406
K0
Kl
K2
K3
K4
K5
K6
K7
-^1 K RAM IN PAGE 0-3
6530-002 (ROM) WHICH
CONTAINS KIM-I MONITOR
VECTOR SELECT
Vector Selection
FIGURE 6.3
78
CHAPTER 7
WARRANTY AND SERVICE
Should you experience difficulty with your KIM-1 module and
be unable to diagnose or correct the problem, you may return the unit
to MOS Technology, Inc. for repair.
7. 1 IN- WARRANTY SER VICE
All KIM series Microcomputer Modules are warranted by
MOS Technology, Inc. against defects in workmanship and materials
for a period of ninety (90) days from date of delivery. During the
warranty period, MOS Technology, Inc. will repair or, at its option,
replace at no charge components that prove to be defective provided
that the module is returned, shipping prepaid, to:
KIM Customer Service Department
MOS Technology, Inc.
950 Rittenhouse Road
Norristown, Pennsylvania 19401
This warranty does not apply if the module has been damaged by accident
or misuse, or as a result of repairs or modifications made by other than
authorized personnel at the above captioned service facility.
No other warranty is expressed or implied, MOS Technology, Inc. is
not liable for consequential damages.
79
7. 2 OUT-OF- WARRANTY SER VICE
Beyond the ninety (90) day warranty period, KIM modules will be
repaired for a reasonable service fee. All service work performed by
MOS Technology, Inc. beyond the warranty period is warranted for an
additional ninety (90) day period after shipment of the repaired module.
7. J POLICY ON CHANGES
All KIM series modules are sold on the basis of descriptive
specifications in effect at the time of sale. MOS Technology, Inc.
shall have no obligation to modify or update products once sold.
MOS Technology, Inc. reserves the right to make periodic changes or
improvements to any KIM series module.
7. 4 SHIPPING INSTR UCTIONS
It is the customer's responsibility to return the KIM series
module with shipping charges prepaid to the above captioned service
facility .
For in-warranty service, the KIM module will be returned to the
customer, shipping prepaid, by the fastest economical carrier.
For out-of-warranty service, the customer will pay for shipping
charges both ways. The repaired KIM module will be returned to the
customer C.O.D. unless the repairs and shipping charges are prepaid
by the customer.
Please be certain that your KIM module is safely packaged when
returning it to the above captioned service facility.
80
APPENDIX A
PA RT
1.
Ul
1
6502 Microprocessor
2.
U2
1
6530 ROM RAM I/O Chip-02
3.
U3
1
6530 ROM RAM I/O Chip-03
4.
U5 through U12
8
6102 RAM 500ns Acc,0ns
5.
U18 through U23
6
7 SEG .3" Red Display
6.
U25
1
556 Timer IC
7.
U27
1
565 Phase Lock Loop
8.
U28
1
311 Comparator
9.
U24
1
74145 BCD Decoder IC
10.
U13 & U14
2
74125 TRI STATE Buffer
11.
U15
1
7400 Quad Nand IC
12.
U16
1
7404 Hex Inverter IC
13.
U17
1
7406 Hex Inv. 0/C IC
14.
U26
1
7438 Quad Nand O/C IC
15.
CR1,2,3,4,&8
5
20 MA. 50v Diode - IN914
16.
CR5, CR6
2
lA 50v Diode - IN4001
17.
CR7
1
6.2v V Z. Diode - IN4735
18.
Q7
1
NPN Transistor B>20, VCE>12 - 2N5371
19.
Ql through Q6
6
PNP Transistor B>20, VCE>6 - 2N5375
20.
R24 & R25
2
hlKii ±10% %w Resistor
21.
Rl,2,3,4, & 6
5
2.2Ki} ±10% !«w Resistor
22.
R34 & R50
2
2.2Kn ±10% %w Resistor
23.
R12-R17, R41-R46
12
l.OKU ±10% %w Resistor
24.
R35 through R40
6
56Qn ±10% %w Resistor
25.
R18-R23, R47
7
220f^ ±10% %w Resistor
26.
R33
1
47fi ±10% W Resistor
27.
R52
1
5 Meg. ±10% %w Resistor
28.
R51
1
30KU ±5% %w Resistor
29.
R7,R8,R9,R10&R11
5
lOKf^ ±5% %w Resistor
30.
R48, R49
2
150f^ ±5% Isw
31.
R26 through R32
7
82fi ±5% V
32.
VRl
1
5Kr2 Potentiometer
33.
C2, C3, C6
3
.22±10i uf.>12 cap
34.
CI, C4
2
lu£+80-10%>12WV Cap
35.
C5
1
.33 uf±10%>12WV Cap
36.
C7,C8,C15,C16,C17
5
.luf+80-10%>12WV Cap
37.
C9, CIO, Cll
3
.0068uf±10%>12WV
38.
C12
1
.047uf±10%>12WV
39.
C13
1
.022uf±10%>12WV
40.
C14
1
.001uf±10%>12WV
41.
1
44 Pin Edge Conn. (Vector //R644)
42.
XI
1
1 MHz XTAL
43.
1
PCB.
44.
1
24 Key KBD
45.
6
Rubber Pads
46.
1
Shipping Bag (Static Free)
47.
1
Shipping Box
48.
1
Hardware Manual
49.
1
Software Manual
50.
1
KIM Manual
51.
1
Warranty Card
52.
1
Wall Chart
53.
2
#2 X % SS Screws (Keyboard)
54.
1
Program Card
55.
CIS
1
1
1 Ht-i -p pap
lUpr UAr
56.
R53
1
33GK V Resistor
57.
U4
1
74LS145 BCD Decoder IC
1
APPENDIX B
KIM-1 PARTS LAYOUT
nnnrinnnnnnni^ni-inr-ii-innT-i
LJl_JL-JL_JS_J':ULJl_il-JLJLJLJLJl_ll_JLJI_!LJLJn
pnnncinnnni-ir-innnni-innnn
U 3
nnnnnnnnnnnnnnnnnnnn
nnnrii-innnnni-n-ii-inr:ii-ii-irjacj,
u 2
■nnnnnnannnonnuHnuauu
iBQannQBg,
UI2
ani-ii-ir-ii-ii-in
nnnnnnnn
U 10
'nnnannan'
pminnQnoizi
u 9
ttnnnnnnn'
nni-inni-irjm
nnr-n-innrTig
U 7
'nnnnnnnn'
g Di-i n n n n g
■nnnnnnnn'
tni-n-ii-inncja
U 5
■nnnnnnnn'
C ]
[ ]
c ]
C UI4 ]
C ]
: :
c •]
c
:
c
C UI3
c
c
— N <yv <y^
(TO: 0:0: (ro: sir era:
rr
B-1
APPENDIX C
IN CASE OF TROUBLE
SYMPTOM : Display Not Lit
1. Test +5 volt power supply. Using a VOM check for +5
volts between Pin E-21 and E-22. Also check for +5
volts between Pin A-A and Pin A-1. KIM-1 power supply
should be set at +5v ± 5%.
2. Test KB/TTY option wiring (Figure 2-4). Pin A-21 should
not be connected to Pin A-V.
3. Make sure decoder is enabled. See Figure 2-2 and insure
that Pin A-K is connected to ground.
4. Depress the reset key and check all other keys to insure
that no key is stuck.
5. Place a VOM between Pin E-21 (+5v) and Pin E-7 (Reset).
Alternately depress and release the reset key checking to
see if the voltage swings from (>4v) to (<lv) .
6. Test Pin E-V (02) with an oscilloscope and insure 1 MHz
operation .
SYMPTOM : Cannot Dump to Audio Tape
Cannot Load From Audio Tape
1. Test +12 volt power supply. Using a VOM check for +12
volts between Pin A-N (+12v) and Pin A-1 (GND) . Set
power supply to +12v t 5%. (See Figure 2-2).
2. Check volume control on the tape recorder (Set at half
way point) .
C-1
3. Make sure that you are using the proper tape output pin.
See Figure 2-3.
4. Check the tape interface circuit by disconnecting the
tape recorder and shorting Pin A-P (Audio Out High) to
Pin A-L (Audio In). Set up KIM-1 monitor to dump a
section of memory. Using an oscilloscope observe data
at Pin E-X (PLL TEST). See Appendix E for correct data
format and calibration procedure.
5. Record voice on a section of tape and play it back to insure
that the tape recorder is working. Connect another tape
recorder to the system or try another cassette.
6. Make sure Status Register (Location OOFl) has been loaded
with data value "00".
7. Make sure Tone Control is set to High.
S YMP T OM : TTY Interface Problems
1, Make sure that Pin A-21 is connected to Pin A-V (Figure 2-4)
to allow TTY operation.
2, Compare the connections on Figure 2-4 with interface
schematics in your TTY manual ( or any other serial
teleprinter ) .
3, Depress the reset key on the KIM-1 keyboard followed by
a rub out character from the TTY.
C-2
APPENDIX E
AUDIO TAPE FORMAT
Data is stored out onto your audio cassette recorder in a specific
format designed to insure an error free recovery. In the unlikely event
that a playback error does occur, several "ERROR DETECTION" methods are
incorporated to warn you of this condition.
Data is transmitted to the tape recorder in the form of serial
"ASCII" encoded characters (seven data bits plus Parity bit). Data
retrieved from the memory is converted into this form by separating each
byte into two half bytes. The half bytes are then converted into their
ASCII equivalents.
Each record transmitted begins with a leader of one hundred "SYN"
characters (ASCII 16) followed by a * character (ASCII 2A) . During
playback, this pattern allows your micro-computer to detect the start of
a valid data record and synchronize to the serial data stream. Following
the *, the record identification number (ID), and starting address low
(SAL) and the starting address high (SAH) are transmitted. The data
specified by the starting (SAL, SAH) and ending limits (EAL, EAH) is
transmitted next followed by a "/" character (ASCII 2F) to indicate the
end of the data portion of the record. Following the "/" two "CHECK-SUM"
bytes are transmitted for comparison with a calculated check-sum number
during playback to further insure that a proper data retrieval has taken
place. Two "EOT" characters (ASCII 04) mark the end of record transmission.
E-1
Each transmitted bit begins with a 3700 hertz tone and ends with
a 2400 hertz tone. "Ones" have the high to low frequency transition
at one-third of the bit period. "Zeros" have the transition at two-
thirds of the period. During playback the 565 phase locked loop locks
to, and tracks these two frequencies producing (through the 311
comparator) a logic "1" pulse of one-third the bit period for a "One".
A pulse two thirds the bit period is likewise produced for a "Zero".
Your microcomputer uses a software controlled algorithm for converting
this signal into eight bit data words.
The frequency shift keyed phase lock loop method of data recover}^'
is relatively insensitive to amplitude and phase variations. The "FREE
RUIJNING" frequency of the phase lock loop has been adjusted at the factory
to a frequency half way between the two data frequencies (called the Center
Frequency). This adjustment is accomplished by strapping Pin A-P (Audio
Out High) to Pin A-L (Audio In) . A program starting at address lA6Byg^
provides the center frequency reference that allows the loop to be
adjusted by potentiometer VRl. Pin E-X (PLL TEST) is monitored with a
voltmeter while the pot is rotated until the voltmeter reading is at the
transition point between a logical "1" (+5v) and "0" (GND) .
THIS ADJUSTMENT HAS BEEN FACTORY PRESET AND SHOULD ONLY REQUIRE
ADJUSTMENT DUE TO COMPONENT REPLACE>IENT !
E-2
2.484 Msec
9 PULSES
7.452 Msec.
2.484 Msec
9 PULSES
2.484Msec
6 PULSES
MminMinMMiiiMiijmiuum
9 PULSES
6 PULSES
— 6 PULSES
MUlMUMUmJWm^^^^L
LOGIC
(0)
LOGIC
(I )
I BIT
100 "SYN"
J 5
L L J
ID SALSAH DATA-^
1 1_J a
I RECORD
/ CKL
CKH
EOT
EOT
Audio Tape Format
FIGURE E-1
E-3
APPENDIX F
PAPER TAPE FORMAT
The paper tape LOAD and DUMP routines store and retrieve data in
a specific format designed to insure error free recovery. Each byte
of data to be stored is converted to two half bytes. The half bytes
(whose possible values are to F ) are translated into their ASCII
equivalents and written out onto paper tape in this form.
Each record outputted begins with a ";" chsiracter (ASCII 3B) to
mark the start of a valid record. The next byte transmitted (18 ) or
(24io) is the number of data bytes contained in the record. The record's
starting address High (1 byte, 2 characters), starting address Lo (1 byte,
2 characters) , and data (24 bytes , 48 characters) follow. Each record is
terminated by the record's check-sum (2 bytes, 4 characters), a carriage
return (ASCII OD) , line feed (ASCII 0A) , and six "NULL" characters
(ASCII 00) .
The last record transmitted has zero data bytes (indicated by ;00).
The starting address field is replaced by a four digit Hex number repre-
senting the total number of data records contained in the transmission,
followed by the records usual check-sum digits. A "XOFF" character ends
the transmission.
;18 FFEEDD C CBBAAOO 9 9887 7 66^5 5443 3 22^1 1 22_3 3445 5667 7889 9 0AFC
;000001 0001
F-1
During a "LOAD" all incoming data is ignored until a ";" character
is received. The receipt of non ASCII data or a mismatch between a
records calculated check-sum and the check-sum read from tape will cause
an error condition to be recognized by KIM. The check-sum is calculated
by adding all data in the record except the ";" character.
The paper tape format described is compatible with all other
MOS Technology, Inc. software support programs.
F-2
APPENDIX G
6502 CHARACTERISTICS
Clocks (01, 02)
The MCS 6502 is supplied with an internal clock generator. The
frequency of this clock is crystal controlled.
Address Bus (Aq-Ai^)
These outputs are TIL compatible, capable of driving one standard
TTL load and 130pf.
Data Bus (DQ-Dy)
Eight pins are used for the data bus. This is a bi-directional bus,
transferring data to and from the device and peripherals. The
outputs are tri-state buffers capable of driving one standard
TTL load and 130pf.
Ready (RDY)
This input signal allows the user to single cycle the microprocessor
on all cycles except write cycles. A negative transition to the low
state during or coincident with phase one (0i) will halt the micro-
processor with the output address lines reflecting the current
address being fetched. This condition will remain through a
subsequent phase two (02) in which the Ready signal is high. This
feature allows microprocessor interfacing with low speed PROMS as
well as fast (max. 2 cycle) Direct Memory Access (DMA). If Ready
is low during a write cycle, it is Ignored until the following
read operation.
G-1
Interrupt Request (IRQ)
This TTL level input requests that an interrupt sequence begin
within the microprocessor. The microprocessor will complete the
current instruction being executed before recognizing the request.
At that time, the interrupt mask bit in the Status Code Register
will be examined. If the interrupt mask flag is not set, the
microprocessor will begin an interrupt sequence. The Program
Counter and Processor Status Register are stored in the stack.
The microprocessor will then set the interrupt mask flag high
so that no further interrupts may occur. At the end of this
cycle, the program counter low will be loaded from address FFFE ,
and program counter high from location FFFF, therefore trans-
ferring program control to the memory vector located at these
addresses. The RDY signal must be in the high state (for control
to the memory vector) located at these addresses. The RDY signal
must be in the high state for any interrupt to be recognized.
A 3K.U external register should be used for proper wire-OR operation.
Non-Maskable Interrupt (NMI)
A negative going edge on this input requests that a non-maskable
interrupt sequence be generated within the microprocessor.
NMI is an unconditional interrupt. Following completion of the
current instruction, the sequence of operations defined for IRQ
will be performed, regardless of the state of the interrupt mask flag.
The vector address loaded into the program counter, low and high,
are locations FFFA and FFFB respectively. The instructions
loaded at these locations causes the microprocessor to branch to
a non-maskable interrupt routine in memory.
NMI also requires an external 3Kn resistor to Vcc for proper
wire-OR operations.
G-2
Inputs IRQ and NMI are hardware interrupts lines that are sampled
during 02 (phase 2) and will begin the appropriate interrupt
routine on the 0^ (phase 1) following the completion of the
current instruction.
Set Overflow Flag (S.O.)
This TTL level input signal allows external control of the
overflow bit in the Status Code Register,
SYNC
This output line is provided to identify those cycles in which
the microprocessor is doing an Op Code fetch. The SYNC line
goes high during 0^ of an Op Code fetch and stays high for the
remainder of that cycle. If the RDY line is pulled low during
the 01 clock pulse in which SYNC went high, the processor will
stop in its current state and will remain in the state until
the RDY line goes high. In this manner, the SYNC signal can be
used to control RDY to cause single Instruction execution.
RESET
This Input is used to reset or start the microprocessor from a
power down condition. During the time that this line is held
low, writing to or from the microprocessor is inhibited. When
a positive edge is detected on the input, the microprocessor
will immediately begin the reset sequence.
After a system initialization time of six clock, cycles, the mask
interrupt flag will be set and the microprocessor will load the
program counter from the memory vector locations FFFC and FFFD.
This is the start location for program control.
After Vcc reaches 4.75 volts in a power up routine, reset must
be held low for at least two clock cycles.
When the reset signal goes high following these two clock cycles,
the microprocessor will proceed with the normal reset procedure
detailed above.
G-3
APPENDIX H
6530 CHARACTERISTICS
The MCS 6530 is designed to operate in conjunction with the MCS 650X
Microprocessor Family. It is comprised of a mask programmable 1024 x 8
ROM, a 64 X 8 static RAM, two software controlled 8 bit bi-directional
data ports allowing direct interfacing between the microprocessor unit
and peripheral devices, and a software programmable interval timer
with interrupt, capable of timing in various intervals from 1 to 262,144
clock periods.
PAO
PA7
I
DATA
BUS
BUFFER
PBO
PB7
DATA
I/O
PERIPHERAL
CONTROL
REGISTER
DATA BUFFER
REGISTER
A
A
A
INTERVAL
TIMER
I
PERIPHERAL
DATA BUFFER
B
ADDRESS
DECODER
CHIP
SELECT
R/W
)--") t^--t 1 1 1 1 1_
DO Dl AO A9 CSI CS2 02 R/W RES
64 X 8
RAM
I K X 8
ROM
I/O
REGISTER
B
T
{ I I
DATA
CONTROL
REGISTER
B
MCS 6530 Block Diagram
FIGURE H.l
H-1
Reset (RES)
During system initialization a Logic "0" on the RES input will
cause a zeroing of all four I/O registers. This in turn will
cause all I/O buses to act as inputs thus protecting external
components from possible damage and erroneous data while the
system is being configured under software control. The Data
Bus Buffers are put into an OFF-STATE during Reset. Interrupt
capability is disabled with the RES signal. The RES signal must
be held low for at least one clock period when reset is required.
Input Clock
The input clock is a system Phase Two clock which can be either
a low level clock (V < 0.4, V > 2.4) or high level clock
i.L In
^^IL < ^IH= ^-^:2)-
Read/Write (R/W)
The R/W signal is supplied by the microprocessor array and is used
to control the transfer of data to and from the microprocessor array
and the MCS 6530. A high on the R/W pin allows the processor to
read (with proper addressing) the data supplied by the MCS 6530.
A low on the R/W pin allows a write (with proper addressing) to
the MCS 6530.
Interrupt Request (IRQ)
The IRQ pin is an interrupt pin from the interval timer. This
same pin, if not used as an interrupt, can be used as a peripheral
I/O pin (PB7) . When used as an interrupt, the pin should be set
up as an input by the data direction register. The pin will be
normally high with a low indicating an interrupt from the MCS 6530.
H-2
Data Bus (Dg-D7 )
The MCS 6530 has eight bi-directional data pins (D0-D7) . These
pins connect to the system's data lines to allow transfer of data
to and from the microprocessor array. The output buffers remain
in the off state except when a Read operation occurs.
Peripheral Data Ports
The MCS 6530-002, MCS 6530-003 both have 15 pins available for
peripheral I/O operations. Each pin is individually software
programmable to act as either an input or an output. The 15
pins are divided into 2 8-bit ports, PA0-PA7 and PB0-PB7. PB6
was used as a chip select and is not available to the user. The
pins are set up as an input by writing a "0" into the corresponding
bit of the data direction register. A "I" into the data direction
register will cause its corresponding bit to be an output. When in
the input mode, the peripheral output buffers are in the "1" state
and a pull-up device acts as less than one TTL load to the periphera
data lines. On a Read operation, the microprocessor unit reads the
peripheral pin. When the peripheral device gets information from
the MCS 6530 it receives data stored in the data register. The
microprocessor will read correct information if the peripheral lines
are greater than 2.0 volts for a "1" and less than 0.8 volts for a
"0" as the peripheral pins are all TTL compatible. Pins PA0 and PB0
are also capable of sourcing 3 ma at 1.5v, thus making them capable
of Darlington drive. Pin PB7 has no internal pull-up (to allow
collector-oring with other devices) .
Address Lines (A0-A9 )
There are 10 address pins. In addition to these 10, there is the
ROM SELECT pin. The above pins, A0-A9 and ROM SELECT, are always
used as addressing pins. There are 2 additional pins which are mask
programmable and can be used either individually or together as
CHIP SELECTS. They are pins PB5 and PB6. When used as peripheral
data pins they cannot be used as chip selects. PB5 was used as a
data pin while PB6 was used as a chip select and is not available
to the user.
H-3
A block diagram of the internal architecture is shown in Figure H-1.
The MCS 6530 is divided into four basic sections, MM, ROM, I/O and TIMER.
The RAM and ROM interface directly with the microprocessor through the
system data bus and address lines. The I/O section consists of 2 8-bit
halves. Each half contains a Data Direction Register (DDR) and an I/O
Register.
ROM IK Byte (8K Bits)
The 8K ROM is in a 1024 x 8 configuration. Address lines A0-A9 ,
as well as RSO are needed to address the entire ROM. With the
addition of CSl and CS2 , seven MCS 6530 's may be addressed, giving
7168 X 8 bits of contiguous ROM.
RAM 64 Bytes (512 Bits)
A 64 X 8 static RAM is contained on the MCS 6530. It is addressed
by A0-A5 (Byte Select), IIS0, A6, A7 , AS, A9 and CSl.
Internal Peripheral Registers
There are four internal registers, two data direction registers
and two peripheral I/O data registers. The two data direction
registers (A side and B side) control the direction of the data
into and out of the peripheral pins. A "1" written into the Data
Direction Register sets up the corresponding peripheral buffer pin
as an output. Therefore, anything then written into the I/O Register
will appear on that corresponding peripheral pin. A "0" written into
the DDR inhibits the output buffer from transmitting data to or from
the I/O Register. For example, a "1" loaded into data direction
register A, position 3, sets up peripheral pin PA3 as an output.
If a "0" had been loaded, PA3 would be configured as an input and
remain in the high state. The two data I/O registers are used to
latch data from the Data Bus during a Write operation until the
peripheral device can read the data supplied by the microprocessor
array .
H-4
During a read operation the microprocessor Is not reading the I/O
Registers but in fact is reading the peripheral data pins. For
the peripheral data pins which are programmed as outputs the
microprocessor will read the corresponding data bits of the I/O
Register. The only way the I/O Register data can be changed Is by
a microprocessor Write operation. The I/O Register is not affected
by a Read of the data on the peripheral pins.
Interval Timer
1 . Cap abilities
The KIM-1 Interval Timer allows the user to specify a preset count
of up to 256io and a clock divide rate of 1, 8, 64 or 1024 by writing
to a memory location. As soon as the write occurs, counting at the
specified rate begins. The timer counts down at the clock frequency
divided by the divide rate. The current timer count may be read at
any time. At the user's option, the timer may be programmed to generate
an interrupt when the counter counts down past zero. When a count of
zero is passed, the divide rate is automatically set to 1 and the
counter continues to count down at the clock rate starting at a count
of FF (-1 in two's complement arithmetic). This allows the user to
determine how many clock cycles have passed since the timer reached
a count of zero. Since the counter never stops, continued counting
down will reach 00 again, then FF, and the count will continue.
2 . Operation
a. Loading the timer
The divide rate and interrupt option enable/disable are programmed
by decoding the least significant address bits. The starting count for
the timer is determined by the value written to that address.
H-5
iLiLerrupL LapaDixity
1704
1
Disabled
1705
8
Disab led
1706
64
Disabled
1 707
1 / U /
1 m /■
Disabled
170C
1
Enabled
170D
8
Enabled
170E
64
Enabled
170F
1024
Enabled
b . Determining the timer status
After timing has begun, reading address location 1707 will provide
the timer status. If the counter has passed the count of zero, bit 7
will be set to 1, otherwise, bit 7 (and all other bits in location 1707)
will be zero. This allows a program to "watch" location 1707 and
determine when the timer has timed out.
c . Reading the count in the timer
If the timer has not counted past zero, reading location 1706 will
provide the current timer count and disable the interrupt option;
reading location 170E will provide the current timer count and enable
the interrupt option. Thus the interrupt option can be changed while
the timer is counting down.
If the timer has counted past zero, reading either memory location
1706 or 170E will restore the divide ratio to its previously programmed
value, disable the interrupt option and leave the timer with its current
count (not the count originally written to the timer). Because the timer
never stops counting, the timer will continue to decrement, pass zero,
set the divide rate to 1, and continue to count down at the clock
frequency, unless new information is written to the timer.
H-6
d. Using the interrupt option
In order to use the interrupt option described above, line PB7
(application connector, pin 15) should be connected to either the
IRQ (Expansion Connector, pin 4) or NMI (Expansion Connector, pin 6)
pin depending on the desired interrupt function. PB7 should be
programmed as in input line (it's normal state after a RESET).
NOTE: If the programmer desires to use PB7 as a normal I/O line,
the programmer is responsible for disabling the timer
interrupt option (by writing or reading address 1706)
so that it does not interfere with normal operation
of PB7. Also, PB7 was designed to be wire-ORed with
other possible interrupt sources; if this is not desired,
a 5 . IK resistor should be used as a pull-up from PB7 to
+5v. (The pull-up should NOT be used if PB7 is connected
to NMI or IRQ.)
H-7
APPENDIX I
KIM-1 PROGRAM LISTINGS
PRGE
RRD
6 6 6 6 66 555555 3 3 3 3 3 3 U
6 5 3 n
6 5 3 ij
666666 555555 333333
6 6 5 3 U U
6 6 5 3: U
6 1. 6 6 6 6 5 55555 33 3 3 3 3 Li U 1'l n
IJ n U U
Ij Ij
Ij Ij
Ij Ij
ij Ij
I j I j Ij I j I j Ij
Ij Ij Ij Ij Li
Ij Ij
Ij Ij
Ij Ij
Ij Ij
Ij Ij
U I j I j Ij
CQPYRIbHT
MDS TECHNDLnGYj IMC
DRTE OCT 13 1975 REV D
6530-003 IS m flUDID CRSSETT TRPE
RECDRDER EHTEhSinh DP THE ERSIC
KIM MDHITDR
IT FERTURES TI..ID BRSIC RDUTIMES
LDRDT-LDRD MEM FROM HUD ID TAPE
DUMPT-STDP MEM nNTG RUDID TRPE
LDRDT
111=0 IGMDRE ID
iri=FF IGH. ID UiE SR FDR STRRT RDDR
ID=ni-FE IGM.ID USE RDDR OH TRPE
DUMPT
ID=On SHOULD HDT BE USED
ID=FR SHOULD HOT EE USED
ID=M1-FE MDRMRL ID RRMGE
SRL LSB STRRT IMG RDDRESS
SRH MSB
ERL LSB EMDIMG RDDRESS
ERH MSB
PHbE
CHRD " LOC
54
CD HE
CRRri
EQLIRTES
SET UP FDR 653n-Liij
I □
b U
bl
6l£'
b 3
b4
65
66
67
6S
69
7
71
U U i.l IJ
SflD
PRDD
SED
REDD
LKIT
LK8T
LK64T
LKKT
LKRDI
LKRUT
=■1:
=■1;
4iJ
41
4 c'
4.:-;
44
45
46
47
47
46
♦='i;Oi:iEF
MRU REG.
653 H BhTh
653 H riHTR HI RECTI DM
653 E DRTR
653 E DRTR DIRECT I DM
nV EY 1 TIME
3 TIME
64 TIME
nV EY 1024 TIME
RERIi TIME nUT EIT
RERIi TIME
hPEh IM PHbE
n I 'v'
EY
E'r
i'' c
OOEF
PCL
♦=♦+1
PRQGRRM CMT LnW
r' 3
nOFO
PCH
♦=♦+1
PRnGRRM CMT HI
74
OOPl
PR EG
♦=♦+1
CURRENT STRTUS REG.
C J
OOFc:
SPUSER
♦ =♦+1
CURPENT STRCK PDINT
76
OOP 3
RCC
♦=♦+1
RCCUMULRTDR
r' i''
OOF 4
YREG
♦=♦+1
Y INDEX
r' C'
OOF 5
XREG
♦=♦+1
X INDEX
y
SI
KIM FIXED RRER IN PRGE
•Z' c
0F6
CHKHI
♦=♦+1
0UF7
CHKSUM
♦=♦+1
34
OOFS
INL
♦ =♦+1
IMP
JT EUFFER
-icr
C' -_'
0F9
INH
♦=♦+1
INPUT EUPPEP
86
OOFR
PQINTL
♦=♦+1
LSE
□F GPEN
CELL
■Z' I
OOFE
RQINTH
♦=♦+1
MSE
OF OPEN
CELL
OOFC
TEMP
♦=♦+1
S'-H
OOFD
TMRX
♦=♦+1
S
OOPE
CHRP
♦ =♦+1
91
OOFF
MODE
<!
♦=♦+1
9£
93
KIM FI
XED
RRER IN
PRGE
94
95
ij 1
♦=I:17E7
96
17E7
CHKL
♦=♦+1
97
17ES
CHKH
♦=♦+1
CHK iUM
9i-;
17E9
SRVX
♦=♦+3
99
17EC
VEE
♦=♦+6
VOLRTILE EXECUTION
17F£
CNTLSU
♦=♦+1
TTY DELRY
01
17F3
CNTH3U
♦=♦+1
TTY DELRY
0£
17F4
TIMH
♦=♦+1
03:
17F5
SRL
♦=♦+1
LOM STRRTING RDDRES
04
17F6
SRH
♦=♦+1
HI STRRTING RDDRESS
05
17P7
ERL
♦=♦+1
LOU END IMG RDDRESS
RRD " LOG CnnE CRRD
1 Ut. 17FS EhH ♦=♦+! HI EMU I Mb RririRESS
107 17F9 in ♦=♦+!
1 OS ;
109 ; INTERRUPT 'v'ECTDRS
110 ;
111 17FH miV ♦=♦+£ STOP VECTOR (STnP = 1 C O::-
11£ 17FC RSTV ♦=♦+£ RST VECTOR
113 17FE IRQV ♦=♦+£ IRQ VECTOR (ERK= ICOO)
1 14 ;
PRGE
RRD " LDC CODE CRPD
1 K
1 7
1 c
1 ■_
II 11
T — .ji i
3
1 1
>
T f ■^ T T
1 1 1 1 1
VDLRTILE
EXECUTIQM ELDCK
1
Tl
•
Til IMP
1' " J ! 1 r
MEM TD TAPE
i_
1
1 ;=
n fl
n I?
ni.'
Til IMPT
1 Tim
"tRD
LORD RESOLUTE IMST
cc
1 c
i_
PTi
pr
CL-
1 1
1 n
VEE
C-Z'
It
05
cLi
3£
19
JSP
INT'v'EE
£4
i_ J
1 ;I
11 !-I
n
c. r
1 TlH
L L' n
"'Ecl7
TUPN DFF DRTRIM PB5
1
•-'I.'
1 7
1 n
SED
C I
1
'J iJ
n _■
Pip
1 Tip
^JtEP
C^rfv'EPT PE7 T^ □UTPUT
C.C'
1 c
1
■J r
P.T\
43
1 7
V T
PEDD
29
1
A.'-'
n i_
1 fl'::'
"■E64
100 CHRPS
31
It
14
H9
16
nUMPTl
LDR
"J; 1 6
SVM CHRp-S
■Z'C
1 •_
1
i o
'-' fl
1 n
1 "P
OUTCHT
It
19
CR
DEX
34
It
IR
no
FS
EME
DUMPTl
•-I — '
•1> i'
1 c
1 r
n y
1 Tifl
1 n r-. 1 '_■ n n r^.
;~; Q
1 c
L C
i_ L'
f n
1 Q
1 y
l~ P
□UTCHT
4 fi
P 1
hTi
1 1
1 Tip
ID
□UTPUT ID
41
It
£4
c l_l
61
r?
JSP
□UTET
4 c'
1 c
C l'
ML'
per
r J
i 1
1 Tifl
L lin
■ P 1
n L
ni ITPIIT vThPTTNH
LJ III-' 1 ■-■ 1 nr-. 1 i 1 1
1 c
i
i_ n
.It
1 Q
■J w
□UTETC
RDDPESS
1 c
i
r o
i 1
1 Tiu
Llin
SRH
i ■_
-! fl
-It
1 Q
1 " P
□UTETC
47
48
It
RB
ED
17
■1
riUMPT£
LDR
'v'EE+1
i::HECK FDP LRST
1 c
i
TTl
L- U
r 1
1 "7
1 I
P M P
L 11 r
ERL
IiRTR E't'TE
=; Tl
1 'I
1 '_
■~"Zl
nL'
pp
C P.
1 "7
1 Trfi
Llin
J i
i
'~» l~"
C. J.I
P'-"
r
1 "7
1 1
■"•pr
w T' '_■
ERH
CJ-i
i ■_
:";P
Q 1*1
-'4
J-'
DUMPT4
54
It
41
R'?
£F
LDR
" •'
□UTPUT EMD □F DRTR CHP
It
43
£ ij
7H
19
JSP
□UTCHT
i 'I
i C
nil
P "7
t. r
1 "7
1 Tiu
l_ lin
CHKL
LRST E'l'TE MRS BEEh
■J i
i c
i
C 1.1
i 7
J n.
□ UTET
nUT PUT M^M □UTPUT
i c
i c
nil
p '-■
1 "7
1 Tim
L Lin
CHKH
CHKSUM
1 c
i '-
■-rr
l_ IJ
f: 1
C' i
1 P
i 7
1 "P
□ UTET
1' i
6 c'
It
c" -
■-•C
R£
0£
LEX
at. n£
£ CHRP-S
6 3
It
54
R'r"
04
rilJNPT3
LDR
"rt. 04
E^T CHRP
64
It
56
£0
7R
19
JSP
□UTCHT
65
It
5'?
Cfl
DEX
66
It
5R
no
FS
EME
DUMPT3
PRbE
LUL
-■ □ LI h
i~ LI Ci Ti
1 SS
l:E;5C
h3
LDfl
"J
DISPLRV 0000
1 69
135E
t-1 cr
C'
PR
STR
pniHTL
FDR HDRMRL E:^
170
1 S b
ri c
.-1 ._\
FE
STR
POIHTH
171
1 362
4C.
4F IC
J MP
STRRT
74
O Ij
31
S4
■?1
3E:
9 3
R4
95
96
Qy
MM
b 3
?bE
ibE
d EC 17
£0 5E 19
dO Eh 19
411: 33 13
DIJMPT4 JSR
JSP
VEE
□LIT ETC
DRTR EYTE OUTPUT
JSR IMCVEE
JMP DUHPTS
LDRD MEMDRY FROM TRPE
1
1
1
1
1
1
1
1
1
13
71
OF 19
h9 311
311 EC 17
3 33 1 9
:7E
R9
4C
:7ri
311
EF
17
■ 3
RD
71
13
3D
FO
1 7
1 3 b
RD
i' C
13
1 31 'M
3D
1^1
17
;3C
R9
:3E
3D
43
17
;91
R9
FF
1 9
3D
E9
17
TRE .WDRD
LDRDT LDR
STR
JSR
LDR
STR
LDR
STR
LDR
STR
LDR
STR
LDR
STR
SYNC
LDRD 13
iJjSD
VEE
I NT VEE
',;:i;4C
VEE+3
TRE
VEB+4
TRE+1
VEE +5
"J; 07
SED
SRV>^
I MIT VDLRTILE EXECUTIDM
ELDCK WITH STR RBS.
JMP TYPE RTRM
RESET PE=:=0 aiRTR IN''
CLERR SRVY FDR SYNC RRER
3
1
3 '-' 6
3
41
IR
SYNCl
JSR
RDEIT
SET H BIT
3 1
1
3 99
4E
E9
17
LSR
SRVX
SHI^T BIT IHTD CHRP
1
3 9 C
OD
E9
17
□ RR
SRVX
3 3
1
39^^
3D
E9
17
STR
SRVX
3 04
1
5R3
RD
E9
17
LDR
SRVX
GET NEW CHRP
1
3P5
C9
16
C:MP
"Jib
SYN CHRP
3 Ob
1
3R7
ri
ED
EME
SYHCl
3 07
3 03
1
5R9
R£
OR
LDX
"i;OR
TEST FDR 10 3YN CHRPS
3 09
1
3HB
3
34
IR
SYNC 3
JSR
RDCHT
3 1
1
3 RE
C9
16
CMP
"1;16
3 1 1
1
3E0
DO
DF
EHE
iYHC
IF NDT 10 CHFiR RE- SYNC
313
1
3E3
CR
DEX
3 1 :3
1
5E3
DO
Fb
EHE
SYHC3
3 1 4
n
315
£lb
1
3B5
c L'
34
IH
LDRDT4
JSR
RDCHT
LGDK FDR STRRT OF
317
1
5P3
C 9
3R
CMP
a ■■■ ♦
DRTR CHRP
1
3ER
^ Ij
06
BEO
LORD 1 1
3 1 9
1
5 PC
C9
16
CMP'
":f 16
IF HOT ♦ SHDULD EE SYN
CRRD
LDC
CD HE
ChPD
PhGE
d d
19 EE
DO
Dl
EME
St MO
ddl
1
riC
FO
F3
EEQ
LDRDT4
C C
1
3Cd
2
F3
19
LQRDl 1
■JSR
RDEYT
RERD ID FROM TRPE
£24
1
r:C5
CD
F9
17
OMF'
ID
ODMPRRE i.iITH REQUESTED
-1 -1 cr
1^ iZ.
1
5C8
FO
OD
EEQ
LnRDT5
1
RD
F9
17
LDR
ID
DEFRULT RERD REODRD
1
sen
C9
ij
0:MP
"iOO
RMYI.I.IRY
C C C'
1
EiCF
FO
06
EEQ
LDHDT5
229
1
SDl
C9
FF
OMR
"SFF
DEFRULT FF IGMDR SR DM
£ 3 1 j
1
3113
FO
17
EEQ
LDRDTb
TRPE
2 3 1
1
5115
DO
90:
ENE
LDRDT
1
£117
2
F3
19
LDRDTS
JSR
RDEYT
GET SR FROM TRPE
234
1
5DH
2 Ij
40
19
JSR
OHKT
■-, --1 CJ
1
5Dri
;E:D
ED
1 7
STR
vEE+l
SRVX IN VEE+l J 2
2 36
1
5E0
2
F3
1 9
JSR
RDEYT
1
E:E3
£
40
1 9
JSR
OHKT
£ 3;=;
1
BE 6
8D
EE
1 7
STR
VEE+2
23'?
1
5E9
40
F3
IS
JMP
LDRDT7
24
£41
1
3EC
2
F3
1 9
LnRDT6
JSR
RDEYT
GET SR EUT IGMORE
£4£
13EF
2
40
19
JSR
OHKT
£43
1
E;F2
2
F3
1 9
JSR
RDEYT
£44
1
5F5
2
40
1 9
JSR
OHKT
£45
246
|!
247
1
E;FS
h2
02
LnRDT7
LDX
":I:02
GET £ CHRRS
248
13FH
2
24
IR
LORD 13
JSR
RDCHT
GET OHRR (K':'
£49
1
EiFD
09
2F
OMR
LDDK FDR LRST CHRP
£50
lyFF
FO
14
EEQ
LDRDT 8
£51
1
E-Ol
2
IR
J SR
PROKT
DM VERT TD HEX
C JC
1
E* 04
DO
£ 3
EME
LDRDT9
Y=l MDM-HEX OHRR
-I cr
C ■_' Z'
1 y 06
OR
DEX
254
-1 ETC-
19 07
DO
F 1
EME
LORD 13
256
1 9 09
2
40
1 '"^
JSR
OHKT
ODMPUTE OHEOKSUM
C _l I
1 9 UC
40
EO
1 (■
JMP
VEE
SRVX DRTR IM MEMORY
19 OF
2
ER
1 '-f
LORD 12
JSR
I MOV EE
IMOREMEMT DRTR pniMTEP
259
1
?12
40
13
JMP
LDRDT7
2 6 IJ
£61
1
E'15
2 Ij
F3
1 9
LDRDTS
JSP
RDEYT
EMD DP DRTR OaMPRRE OH^
26£
1
513
OD
E7
OMP
OHKL
£ 6- 3
1
E-IE
Ii
OC:
EME
LnHDT9
264
1
5111
2
F3
1 9
JSR
RDEYT
£65
I
5 2 1 j
OD
E'E'
17
OMP
OHKH
£66
1
^ £
DO
04
ENE
LDRDT9
£6?"
1
525
R9
LDR
"t
MQPMRL EXIT
2 6' 3
1
?£7
FO
02
EEQ
LORD 1
269
270
1
5 £9
R9
FF
L0RDT9
LDR
"tpF
ERROR EXIT
271
1
5£E
O •_'
FR
LORD 10
STR
PniMTL
I:hRD i
r LDC
ODDE
ORRD
C I c
19211
ric
1-1 ._i
FE
STR
PDIMTH
192F
40
4F
10
JMP
STRRT
PRGE
£74
PRGE
:HRri
LDC
CODE
ChRD
. r O
. I'' I'"
. r C'
iUERDUTINES FDLLDI..J
279
:SIJE
TD MOVE SR TD VEE+15 3
£31
19::
C
HD
F5
17
INTVEE
LDfl
SRL
19-:
c-
_i
8D
Ell
17
STfl
VEE+1
c y
19::
Hli
F6
17
LDR
SRH
£S4
19::
B
80
EE
1 7
STR
VEE+3
-1 i-i C
c o_'
19:
E
fl9
6
LDR
"'fbU RTS IHST
£86
194
8D
EF
17
:STR
VEE+3
c o r'
194
R9
LDR
"i;0 CLERR CHKSUM RRER
C O 'l'
194
8D
E7
17
:::TR
CHKL
£89
1948
8D
E3
17
STR
chk:h
£.9 Ci
194B
6
RT3
£91
?
£9£
COMPUTE i::HK:::IJM FQR TRPE LORD
£93
RTH
USES Y TO SRVX R
£94
£95
194
f:
R8
CHKT
TRY
£96
194D
18
CLC
£9?
194E
60
E7
17
R DC
CHKL
£93
195
1
3D
E7
1 7
:STR
CHKL
£99
195
4
RD
E8
17
LDR
CHKH
3 n
195
i'
69
IJ
R DC
"'J
3i;il
195
8D
E8
17
:iTR
CHKH
3 n£
195
c
98
TVR
3 ij3
195
D
6 U
RT3
3 04
3 i:i5
□ LIT PUT ariE BYTE USE V
]: Ub
3 IJ?
TO
SRVX BYTE
3 08
195
E
£0
4C
19
□UTBTC
JSR
CHKT CDMP CHKSUM
3 fiy
19-:
1
h8
□ UTET
TRY
Sh'v'X DhTR BYTE
3 1 n
196
4h
LSP
R SHIFT OFF LSD
311
196
4h
LSR
R
31£
1964
4h
LSR
R
3 1 3
196
4R
LSR
R
314
196
6
3 IJ
6F
19
JSR
HEX OUT OUT PUT MSD
315
196
Hi-i
TYR
3 1 6
196H
3
6F
19
JSR
HEYDUT OUT PUT LSD
317
196
II
9 3
TYR
5 1 9
19t
p
6
PTS
3 1 9
5 £
1
COM
,'ERT LSD OF H TO RSCII
531
RHD
□UTPUT TD TRPE
1961=^
IJF
HEKOUT
RHD
334
1 ?7
1
C9
OR
CMP
Oh
_• C
197
18
CLC
3 c'6
197
4
?. i"i
03
BM I
HEXl
197
69
07
RDC
4-1; 07
PhGE
1 LI
CflPD
LDC
197'
CODE
3
CRPD
he:ki
4
41
4d
43
44
45
46
47
4S
49
5
51
197H
197II
193
19
19
19
19
193
193E
1991
1994
1995
1997
199H
199D
B
3E E9
3C. ER
RO 03
3 9E
4R
E LI A
3
4C
3
3' fi
9E
91
C4
i:;4
19
19
19
19
DO EE
RE E9 1"
RC ER r
6 IJ
tr ■-■
■_' Z'
199E
R3
Ol-h
54
19R0
43
19R1
3C
47
17
19R4
1
FE
-1 1
19R6
R9
7E
cr.-i
_) -^i
19R3
3D
44
17
5y
19RE
Hy
R7
6
19RD
3D
43
17
61
19E0
3C
47
17
63
19E3
1
FE
if,
19E5
R9
7E
64
19E7
3D
44
17
65
19ER
R9
C (■
66i
19EC:
3D
43
17
67
19EF
CR
63
1 9 1 J
DO
DP
69
19C3
6' 3
70
19C3
6
71
r c
i' z>
74
1" J
i' T!'
19C4
R£
06
i' r'
1906
43
i' O
19C7
30
47
17
79
19C:R
1
PE
17 DUTOI
17
19 OHTl
OHTc
CHT'
□ ME
□ NEl
□riE3
:PD1
RDL
"'1.3
□ UTPIJT
TO TRPE □ME RSOII
OHRP
USE SU
E-'S GME + ZRD
STX
SR'v'X
STY
SR VX+1
L DY
at 03
STRPT EIT
JSP
□ ME
LSR
R
GET DRTR EIT
E iSS
0HT3
J SR
□ NE
DRTR EIT=1
JpIP
0HT3
JS' R
ZRD
DRTR EIT=0
JSR
ZRO
DEY
EHE
OHTl
L DX
SR vX
LDY
SRVX+1
RTS
□UTPUT
1 Tn
TRPE
9 PULS
ES 133
f'lIOP^SEO EROH
LDX
09
PHR
S R X R
E T T
OLKRDI
WRIT FOR TIME
EF'I
L.' ' i—
□ MEl
L- i~' '1
" 1 36
STR
CLKIT
1 DR
"'i;R7
"TR
SED
SET PE7=1
F; T T
OLKRDI
EPI
L.' 1 1
□ HE3
L DH
" 1 36
^TR
— - 1 n
OLKIT
LDR
"'£37
■J- 1 n
SED
RESET PE7=0
DEX
ENF
□MEl
PLR
RTS
□UTPUT
TO
TRPE
fZ^ PI ||_ "
ES 3 07
MIOPOSEO EROH
LDX
iri. 06
PHR
SRVX R
EIT
OLKRDI
EPL
ZROl
1 1
Lac
i_
□ HE
-
19CC
99
\~\ ■ -;
-
31
19 CE
9D
44
17
-
19111
h9
H?
-
19D3
till
43
17
-
o4
19D6
-:c
47
17
-
19119
1
EE
-
•56
19DE
h9
r: 3
r'
19Dri
911
44
1 7
1 9E0
99
19Ec.'
y D
43
1 7
9
19E5
CR
91
19E6
D
DE
19E'3
63
9 "i
19E9
6
CHR'D
94
9 J
96
97
9fl
9'^
4
4 01
4 03
4 03
4 04
4 05
4 06
4 07
4 03
4 09
410
411
413
413
414
415
416
417
413
419
43
431
433
434
435
436
4 37
433
439
43
431
19EH
19Eri
19EF
19EP
19Hy
19E6
19F9
19 PC
19FF
1 R
1h03
1R04
1 R 06
1RU3
IR OR
IHUC
IROD
IROF
1 R 1
IRU
1R13
1H13
1R15
1R16
1R19
IRIH
1 R 1 C
IHIF
EE ED 17
D Ci 3
EE EE 17
1^,
) 34 IR
) 1 H
i 34 IR
) IJ U 1 H
U9 JO
30 IE
C9 47
10 1 H
C9 4
3 3
13
69 09
3H
3R
3h
3H
RO 04
3R
3E E9 17
ZRD3
RriEVT
PRCKT
PRCKTc
DO F9
RD E9 17
H IJ Ij
LBR
"195
3TR
CLKIT
LDR
"•tR7
3Th
CBD
BIT
CLk:RDI
BPL
ZRD3
lDR
" 1 95
3TR
CLKIT
LIiR
"■1:37
STR
CBD
DEX
"ENF
ZPDl
PLR
PTC
'UB
TO INC V
INC
VEB + 1
ENE
IhCVEl
INC
VEE+3
RTi
CUE
TD RERD
JSP
RDCHT
J CP
PRCKT
JCR
RDCHT
J CP'
PRCKT
PTC
PRCt
( R=RCCII
RC HEX DRTR
CMP
"■E3
EMI
FRCKT3
CMP
":B47
BPL
PRCKT 3
c;MP
"1:4
EMI
PRCKT 1
CLC
hDC
" i 9
RQL
R
RDL
R
RDL
H
ROL
H
LDV
"J; 04
RQL
H
RQL
CRVX
HEY
BME
PRCKT3
LDR
SflVX
LDY
"■f
SET PB7=1
RESET PE7=0
iECTDRE R
EB+1 ^
T = 'v'RLIB HE'
::HRR
HRD "
LQC
:dde
ChRD
4od
1H31
6 LI
RTS
433
iHcc
C 3
PRCKT3
I m
434
1H33
6 iJ
RTS
435
<i
436
<i
GET 1
CHRR FK
4 37
|l
MITH
CHRR IN
433
?
439
1H34
3E
EE
17
RDCHT
3TX
SRVX+3
44
1R37
R3
LI 3
LDX
"to 3
441
1H39
c L'
41
IR
RDCHTl
J 3R
RDEIT
4 43
lH3i:
4E
ER
17
L3R
SRVX+1
4 43
1>93F
on
ER
17
ORR
SRVX+1
444
lH3d
31'
ER
17
SIR
SRVX+1
4 45
1H35
CR
DEX
446
1H36
DO
Fl
EHE
RDCHTl
447
443
1^=133
RD
ER
17
LIiR
SRVX+1
443
1H3B
cR
RDL
H
45
1h3C
4R
L3R
R
451
1H3D
RE
EE
17
LDX
SRVX+3
453
1H4
6 IJ
RTS
453
4 54
THIS
SUE GETS
455
ThPE
RND RETL
4 56
457
1h41
3C
43
17
RDEI T
EIT
SED
4 53
1H44
1
EE
EPL
RDEIT
453
1H46
RD
46
17
LDR
CLKRDT
4 6
1H49
RO
EF
LDY
iJ:i;FF
461
1H4B
46
17
STY
CLK64T
463
463
1H4E
RO
14
LDY
;?tl4
464
1H5U
RDEIT3
DEY
465
1R51
DO
ED
ENE
RDEIT3
4 66
467
1R5:-:
3C
43
17
RDEIT3
EIT
SED
463
1R56
EE
EMI
RDEIT3
469
!i
470
1R53
-;x
SEC
471
1H59
ED
46
17
3 EC
CLKRDT
473
1R5C
RO
EE
LDY
ii-t.FF
4 73
1R5E
;-; r
46
17
3TY
CLK64T
474
475
1R61
RO
07
LDY
"'E 07
476
1H63
RDEI T4
DEY
477
1R64
DO
ED
EHE
RDEIT4
4 73
479
1H66
49
i=F
EDR
430
1R63
39
3
RND
"Ey
451
1R6R
6
RTS
Y=0 VRLID HE>:
Y=l NOT HEX
RERD 3 EITS
GET NEXT DRTR EIT
RIGHT SHIFT CHRR
□R IN SIGN EIT
RERLRCE CHRf^:
MOVE CHRR INTO R
SHIFT OFF PRRITY
MRIT FDR END OF STRRT EIT
GET STRRT EIT TIME
R=356-T1
SET UP TIMER
DELRY 100 MICROS EC
WRIT FDR NEXT STRRT EIT
C 3 5 6 - T 1 - ■:; £ 5 6 - T 3 ::■ = T 3 - T 1
SET UP TIMER FDR NEXT EIT
DELRY 50 MICRDSEC
COMPLEMENT SIGN OF R
MRSK RLL EXCEPT SIGN
HRD
Lnc
CODE
■RRD
483
484
4 85
4 86
437
488
489
4 9
491
49£
4 93
lR6t;
R9
494
1R6D
SD
48
495
1 R 7
R9
BF
496
1 R78
4 3
497
1 H7S
P
47
499
1 h78
lilt *— <
1 I'l
c
5
1 h7R
h9
9R
5 1
1 R7C
8D
44
5 08
1R7F
R9
R7
5 03
1h81
311
48
5 04
5 i:i5
1R84
cC
47
5 06
1R87
1
FE
5 07
1R89
R9
9R
5 OS
lH8t'
8D
44
5 09
1h3E
H9
5 1
1 H 9
3D
42
511
1h93
4C
■"7 Cj
518
5 1 3
S 1 4
515
516
1R96
517
lEFR
6E
IR
518
lEFC
6E
IR
519
lEFE
6E
IH
52
PL LI
PLLc
miFc
RSTP.;
iRQp;
DiRGriasric
MEMORV
PLLCRL
PLLCRL OUTPUT 166 MICPaSEC
PULSE STRING
PLLCRL LDR
STR
LDR
STR
BIT
EPL
LDR
STR
LDR
STR
BIT
EPL
LDR
STR
LDR
STR
. IMP
":l;87
SBD
^MiEF
PEDD
tSLKRDI
PLLl
j;l54
CLKIT
i-i:R7
SED
CLKRDI
PLL2
"154
CLKIT
"•f87
SED
PLLl
TMPfj OFF DRTIN pB5=1
CONVERT PB7 TO OUTPUT
MR IT 166 NICRD SEi
GUTFUT PB7=1
fB7 =
INTERRUPTS PRGE 87
+ 01^4 RESERVED FOR TEST
.I..IORD PLLCRL
. WORD PLLCRL
. WORD PLLCRL
PRGE
;flRri " LOC
Ll4
ij
4U
41
42
43
CD HE
CflRH
S
666666
6 6
6 S
666666
I. I. I. I. I I
Ill nil III
I nil 1 1 II I
IJ IJ IJ U IJ
IJ
III
Ci
n n fi I"! n
IJ IJ IJ IJ
n I Nj IJ
PRGE 1
CflRD
CnPVRIbHT
MOS TECHNDLDGV IHC.
IiRTE DCT 13 1975 REV E
KIM :TTY IMTERFRCE
:KEYBDflRD IMTERFRCE
:? SEG 6 DIGIT niSPLRV
TTV CMDS:
G GOEXEC
CR OPEN NEXT CELL
LF DPEN PREV. CELL
MOD I FY OPEN CELL
SP DP EH NEW CELL
L LORD (OBJECT FORMhT)
Q BLIMP FROM DPEN CELL RBBR TD HI LIMIT
RO RUE OUT - RETURN TO STRRT tKIM'
c. CRLL ILLEGAL CHRP RRE IGNOPED:'
KEYBDRRD CMDC:
RBIiR SETS MODE TO MDIUFY CELL hBDRESS
DRTR SETS MODE TO MODIFY DRTR IN OPEN CELL
STEP INCREMENTS TD NEXT CELL
RST SYSTEM RESET
RUN GOEXEC
STOP JlCOCi CRN BE LGhDED INTO NMIV TO
USE STOP FERTURE
PC DISPLRY PC
CLOCK IS NOT DISRBLED IN SIGMR 1
PRGE 16
CRRD i
534
LOC
1 C U ij
cnriE
CRRD
♦ ='ElCnLi
537
IC
1 j Ij
35
F3
SR''
•'E
STR
RCC
KIM ENTRY VI R
533
IC
ij3
6ti
PLR
□P BRK (IRQ;'
539
n:
03
55
Fl
STR
PREG
59i:i
If
05
63
SR'-
■'El
PLR
KIM ENTRY VI R
591
ic
06
1-1 c-
O
EF
STR
PCL
592
ic
03
S'5
FR
STR
PDINTL
593
ic
OR
6 8
PLR
594
ic
OB
FO
STR
PCH
595
IL
on
i- c
FE
STR
PDIMTH
596
ic
OF
34
F4
SR'-
■'E3
STY
YREG
59?
IC
11
36
F5
st;>=;
XREb
5 93
IC
13
EA
TSX
599
IC
14
St.
F£
STK
SPUSER
fc.
IC
16
30
IE
JSR
IhlTS
6 Ij 1
IC
19
4C
4F
IC
J^'IP
STRRT
fc. IJc."
6 03
6 04
6 05
6 06
6 0?
6 03
6 09
6 1
611
612
613
614
615
616
61?
6 1 3
619
62
621
622
623
624
625
626
62?
623!
629
6 3
631
632
6 3'3
634
635
:r ldst::'
ICIC 6C FR 17 NMIT JMP CNMIV::' MDN-MRSKRELE INTERRUPT TRRP
ICIF 6C FE 1? IRQT JMP aPQV::- INTERRUPT TRRP
R2
FF
RST
LEK
iJtPF
KIM ENTRY
V I R
RST
1C24
9h
TXS
1C25
c!6
pp
st;«:
SPUSER
1C2?
20
33 IE
JSR
I NITS
IC
2R
R9
FF
IC
2C
3n
F3
IC
2F
R9
01
IC
31
2C
4
IC
34
no
19
IC
36
3
F9
IC
R9
FC
IC
3R
13
IC
3E
69
01
IC
3D
90
3
IC
3F
EE
F3
IC
42
RC
4
IC
45
10
F3
IC
47
SB
F2
IC
4R
R2
03
IC
4C
6R
1? ntTi
nET:;
DETCPS LnR
STR
LnR
BIT
ENE
EMI
LnR
CLC
Rnc
ECC
I NC
Ln'-i
EPL
STR
Lnx
JSR
DET^
"■i;FF
CNTH3
"tOl
SRn
STRRT
nETl
itJFC
"tOl
DET2
CNTH3
SRn
nET 3
CNTL3
its 03
GET 5
COUNT STRRT BIT
ZERO CNTH3
MRSK HI aPnER BITS
TEST
KEYEn SSI. I TEST
STRRT BIT TEST
THIS LDOP COUNTS
THE STRRT BIT TIME
CHECK FDR ENE QF STRRT BIT
GET REST OF THE CHRP
TEST CHRP HERE
MRKE TTY--KE SELECTION
PRGE
CRRIi a
LDC
CRRD
61
6
1 r
4F
JSR
T N T T 1
1111 1 1
b'3
r'
1 r
•"•'I' fl 1
E TT
■"• Pi Tl
b--
E NF
T T 'v' It' V
1 1 J r. p
6 4 1 j
1 I
_.p
1 tr
rPI F
r. I_ r
641
1 r
5C
rti—
U n
1 EV
64
iC
1 r
5E
'-' 1
1 p
JSR
P P T •"• T
64
If
61
n r
1 Tl
1 u
1 MP
"Mniii 1
644
645
1 r
64
n
fl fl
f l Puip
1 flH
If Ji l_l M
64
1 f
6i 6
CO
r o
T ^•4I
1 rtL
64
IC
68
i-rcr
C Q
r r
STR
T MU
64S
IC
6R
5fl
IE
RERD
JSR
GETCH
649
1 r
6Ti
T' L'
C9
01
r MP
65
Ij
1 r
1 —
6F
r U
l"t ill
IJ o
u P 'j-f
1 1 1 r\t>
65
1
1 r
"7 1
1 i.
C U
n L-
1 p
i r
1 "C"
■_' n.
PCiPlt'
r nL r-.
65
I r
74
4L-
11 h'
1 Tl
1 MP
~ iTj M
65
65
4
MhT N
p n T T M P
r.U 1 lilt
65
c
RNE
ri T " P 1 fl v
65
6
65
7
i' r
■-' n
i_ u
1 Q
1 p
1 r
1 1 1 1 : X^'
1 "P
u- n 11 LI
65
1 n
Tl f 1
Ti ■"'
L'
PNP
~- T Q P T
•1- 1 nr. 1
65
t
iZiO
n y
IJ 1
TT't'KP 1
L- vn
^ 'I- l"! 1
ir t IJ 1
6 if
ic
7E
C.L.
■1 i"r
1 1
EIT
LJ Tl
/; rill
6 1
1
SI
FO
C: C
EEQ
STRRT
66
E'
19
IF
1 "P
SCRND
6 €
. I
r L'
r H
EFP
JL' ^
1 1 1 r-. b 1
664
1 Q
1 P
1 r
ISR
.:• I-- n 1 1 11
6t
cr
_i
P,V.
P fi
c. r
EFm
i' p
T T 'v' P 1
1 1 1 r-.p 1
6 1
66
6
r''
■-' ri
C' r1
1 P
i r
JSR
uFTk'FV
i.:it 1 r-.C. 1
6 1
'H 11
l~ •
r MP
p 1 _i
6 li:
Q
r^i
1 n
P P
C' C<
EPl
1 nr. 1
:
!~ '-j
1 J.
("MP
•"■'I 1 A
6 7
1
:
IT fi
r L'
■4-
DC'--.
C' r- r- hi Tl
6 7
c
:
~
Q
i n
1 u
L- 1 ir
J h iT- i ri
6 7"
MM
r IJ
1 .
iZi Tt Tl O M
HullKi'l
67
4
\_. y
1 1
TMP
.' 'I- 1 1
t 1 1
67
c
;
QP
:^c.
C Tl
d. U
P Pfl
P t W
Tl iZi T ill M
11 n 1 Hn
r
^;,
H IJ
l_. 'fH
1 c
CMP
.ii.iT- 1 -"i
" t 1 P
67
I'
. I
QP
1 ■_
p fl
-■C
i_ ~
t' d
"TFP
J- 1 p r
67
R4
I
CMP
■"■ I' 1 o
6 7
. i-
h6
p fl
-' 1
EEQ
O U i'
6 '~
HS'
H SL
n
6 c
1
,;
R"!
It -- < —
fl
n
6
c
M - 1
n j-t_
n
6 c
RB
OR
RSL
R
4
RC
FC
STR
TEMP
6
RE
R.i
04
LEX
":i.n4
6 G
E
H4
FF
IiRTRl
LEY
MODE
6 c
Ed
DO
OR
EME
RDDR
PRT CR LF
TYPE OUT KIM
CLERR INPUT EUFFER
GET CHRP
FDR KEY EDRRD
IF H=0 MD KEY
DISPLRY PC
REDR MDDE=1
ERTR MaEE=l
STEP
RUN
SHIFT CHRP INTO HIGH
ORDER NIEELE
STORE IN TEMP
TEST MODE 1=RDDR
MODE^O DRTR
PHGE
CRRIi i
'1 9'?
iJ
01
U c
3
04
05
06
07
08
0'?
1
1 1
Id
13
LOG
IFfc
iF6£
IF 6 3
1F65
1F67
1F69
CODE
H4 FC
6 ri
Eb fh
ri 03
E6 FE
6 IJ
CflRD
LDV
RTS
IN OPT INC
BNE
INC
INCPTc: RTS
TEMP
RESTORE
SUE TO INCREMENT POINT
PDINTL
INCPTc'
POINTH
GET KEY FROM KEY EORRD
RETURN I...IITH R=KEY VRLUE
R GT. 15 THEN ILLEGRL OR NO KEY
14
1F6R
h3
3 1
|-->ETKEY
L DX
"SSI
iTHRT HT digit
15
1 F6C
R
01
GETKE5
LDY
"J 01
GET 1 ROM
16
1F6E
3
03 1 F
JSR
ONEKEY
17
1F71
no
07
BNE
KEYIN
R=0 NO KEY
18
1F73
EO
c r"
CPX
"■tc! ('
TEST FOR DIGT 3
1 9
1 F75
D
F5
BNE
'GETKE5
c IJ
1 F77
R9
15
LDR
"'515
15=N0 KEY
31
1 F79
6
RTS
iZ. c
1 F7R
H
FF
KEYI N
LDY
"-EFF
C Z'
1 F7C
OR
KEY INI
RSL
fl
i-HIFT LEFT
34
1 F7ri
B
03
ECS
KEYIN3
UNTIL Y=KEY NUM
35
1 F7F
C 3
I NY
36
1 F8
1
PR
EPL
KEY INI
c r'
1 Fdd.
8R
KEY IN3
TXR
c c'
1 F83
39
OF
RND
"JOF
MRSK MSD
39
1 Fd5
4R
LSR
H
DIV BY 3
3
IF 36
RR
TRX
31
1F37
9 i-i
TYR
1F33
1 IJ
03
BPL
KEYIN4
1F8R
13
KEYIN3
CLC
34
1F3B
69
07
RDC
"'E 07
MULT (X-lJ TIMES
~i CT
Z'
IFyl!
Cfi
KEYIN4
DEX
1F8E
DO
FR
BNE
KEY INS
Z' t
1 F9
6 iJ
RTS
3 9
«I
SUE
TO COMPUTE C
HECK SUM
4
>!
41
1F91
18
CHK
CLC
43
1F93
65
F7
RDC
CHK SUM
43
1F94
35
F7
STR
CHKSUM
44
1F96
R5
F6
LDR
CHKHI
45
1F98
69
RDC
ii i
46
1F9R
35
F6
STR
CHKHI
47
1F9C
6
RTS
43
49
GET
3 HEX CHRR-' S
RND PRCK
5
INTO
INL RND INH
ChRD LDC CCIDE CRK'D
1151 ; ■■; PPExEF'VED V '=:ETiJf^'NEr! =
115d ; NQH HEX CHh'=^' !.iiILL BE LDRLED R": NERf^'E^:! HEX EQU
54
IFyli
P I'l
5R
IE
EETEVT .rc'
RFTC
H
._'
1 fh u
c IJ
HL
IF
J IF
pRCk
56
IFH--;
■-' IJ
jR
IE
J S'R
EETC
H
J f'
IFRR
E'
hC
IP
J SF
PRCK
5 '-'
1FR9
R5
EE;
LDR
IHL
59
IFRE
6 IJ
FTS
6 1
::HIFT
CHRP IM R
I ^^ T □
E. iz!
iriL RHD IMH
E E'
64
IFflC
C'-*
3 1 J
PRCK
CflP
;?'i.30
l-relk fof' he
65
1 FRE
3 IJ
IE
En I
UP ERIE
1 EE
i": 9
47
CflP
-147
NGT HE.-, t.-. IT
67
IFBE
1 ij
1 7
EPL
UPDRTE
El tl
1 EE 4
C' 9
4
HEXr-^UM
Cr-IF
"t4u
CnUvERT TG HEX
6 9
1 F E;
3
IJ 3
E''1I
UPDRTE
7
1FB3
13
HEXRLP
CLC
71
1 FE9
6 9
09
R DC
'.i 'E 9
1 FEE
E'R
UPDRTE
FDL
H
7 '3
1 EEC
PR
RCIL
H
74
IFE D
ER
POL
R
~? cr
I-
IFBE
ER
POL
R
7"
IFEF
R IJ
04
LDY
SHIFT IHTQ J.-D EUFTER
i"' r"
1 EC 1
ER
UPDRTl
PDL
R
I'' C'
IFCd
E'6
F3
RQL
IhL
79
1FC4
c'6
F9
RQL
INH
8
1FC6
DEY
31
IFCT
no
FS
ENE
UPDRTl
IF 09
H9
LDR
;-i;on
R=0 IF HEX HUM
IFCB
6
IJPDRTS
RTS
34
5
IFCC
R5
F3
□PEN
LliR
I ML
MGVE I •■a BUFFER TD PGIHT
36
IFCE
Fh
STR
PDIHTL
IFDO
R5
F9
LDH
IMH
TRRNSFER INH- PGINTH
IFDE
'-' ^
FB
STR
PQIHTH
E; R
lFri4
6
RTS
1 1 9 ;
1191 ;
1193 ; EHE OF SUBRnUTINES
KRhE
chrd
LDC
cariE
::nRD
194
195
196
1 97
lFIi5
IJ n
1 '^7
J. -■ I
1 FDb
197
1 Fri7
IJ
197
1 FDS
197
lFri9
197
IFIiR
197
IFDE
OR
197
IFDC
on
197
IFHD
411
1 98
IFEO
c Ll
193
IFEl
13
193
IFEE
c
C
1 93
1FE5
£0
193
1 FE6
1 3
199
£Ci 1
E'lJd
1FE7
EF
£ UE'
1FE3
36
ECiE'
1FE9
HE
£n£
IFEfl
CF
E E'
IFEB
E6
cUE
1 FEC
ED
E'OE
1 FED
FD
E ij E
1 FEE
E 1 j 3
Eij4
1 FEF
FF
E 04
IFFO
EF
E ij4
1 FF 1
F7
£04
IFFE
'^C
£04
IFF 3
E9
£04
1FF4
EE
£04
1FF5
F9
£04
IFF 6
Fl
TDP
49 4E
r -1 .A c
TRELE
TRELES
.BYTE 3; I
IJ J 'i; J 't J '£ 1 J J 'E j t j 't OR j 't U D j ' M I K
BYTE
:i:l3i. ■• RRE -
Jlx
BYTE
TRELE HEX TD 7
1 £ 3
SBFi.:i;36<'EDE!.:l;CF
SEGMEMT
4 5
J IE 6
■EED
t,
JFE;
BYTE
3 9 R B C n
■EFF 5 :i;EF , :I;F7 ^ iFC , ■I;B9 ^ :f DE :
:I:F9!
F
■EFl
PRbE
CRRD
LDC
CD BE
::RtT'D
£06
£07
£ 03
£ 09
£10
INTERRUPT VEC
£11
ElE
1FF7
♦ = i:lFFR
£ 1 3
IFFR
IC IC
NMIEHT
.I.IDRB NNIT
£14
IFFC
££ IC
R STENT
. WaPD RST
£15
IFFE
IF IC
IRQEHT
.WORD IPQT
£16
. END
END QF MDS-'TECHNGLnGY li
NUMBER DF errors' = O-
:i:^^ RSSEMFLY VERSION 4
NUMBER DF URRNINGS =
SVMBaL ThELE
SYMBOL
VRLUE
LIME IiEFIMED
CRDS::
-REFEPEMCE
flCC
ijOFS
76
5y 7
351
HDriR
ICBE
694
637
ICCS
7 1 j 1
673
RK
lEFE
1 037
1 3
1 Fij4
1 04 1
1 046
CHRR
IJIJFE
9
9 5
951
953
959
9y4
994
CHK
1F91
1141
734
i" — ' C'
741
743
3 U 3
514 399
CHKH
17E3
97
1 53
365
339
399
3 1
CHK HI
F6
o c
755
f 'Z' c
d 1 9
1144 1146
CHKL
17E7
96
15t.
263
C C'
£97
393
CHK SUM
OOF?
-' -'
739
1"
u 1
c'c 1
1143 1143
CHKT
134C
£95
£34
C -Z' {
343
£44
356
3 03
CHTl
1 332
3 3 6
o44
CHT£
19SE
34 1
CHT3
1 99 1
343
34
CLERP
lCt.4
645
3 3
336
CLKKT
1747
65
♦ ♦♦♦
CLKRIH
1 747
66
355
36 1
37:-;
334
493
5 05
CLKPUT
1746
67
459
471
CLKl T
1 744
63
3 5 3
364
331
5 n 1
IT 1-1 1-1
. ( 1 I i-i
CLK64T
1746
64
461
473
CLK3T
1745
6 3
♦ ♦♦♦
CMTH3n
17F3
1 1
6 1 3
633
1 01
1 03ii:
CMTL30
17F3
1
t.35
1 1 £
1 034
carnvD
1 F43
1 035
1 U I- 1
1 074
caMvni
1F5E
1 094
1 095
CRLF
lEE'F
9 3
64
~7t~iC
I o _i
339
DhTR
ICRS
63
♦ ♦♦♦
DRTRM
ICCC
7 04
675
DRTRMl
ICCE
7 05
7 03
DRTRMS
1 cn ij
7 06
699
DhTRI
1 CE
636
693
DRTRE'
ICC 3
697
693
DEHRLF
IEEE
1 033
947
956
DELRY
lEri4
1 1
946
953
986
9 9 U
997
1 IJ Q'3
DETCPS
1 C3R
6 1 £
♦♦♦+•
DETl
1 C3 1
615
617
IIET3
1C43
633
631
riET3
lC3fl
619
634
DEd
lEDD
1 Ij 1 3
1 1 3
1 037
DES
1EE5
1017
1015
IiE4
lEBE
1 1 4
1 0£9
DUMP
11143
i"' f C'
y7y
DUMPT
1 3
131
riUMPTl
1314
131
1 34
rilJMPTS
1333
143
177
BUMPTS
1354
1 6 3
166
riUNPT4
1365
1 1'' 1^
153
nuMPv
IE 01
y r' 3
367
nuMPO
1 D43
731
3 £6
nuMPi
1D4E
735
♦♦♦♦
J. 1 1 1 E' U L
Mi IIP
LINE DEFIMEIi
fii IMP;-'
i. U 1'
81 1
817
til IMP ";
L' '—'1 1 1 — '
i L' it O
834
fll IMP 4
i L' 1 n
3 05
793
_ n "I
1 ':^F'-'
i 06
151
1
1 y X
c n L
1 "^P"^
1 1 r (
105
149
"7 C' O
' C C L'
1 P fi 7
376
361
F P F fM
1 C lL L* 1
1 P1 P
C' C' c
38
1 T P T P 'y' T
1 P'^ri
1 f r LI
1 154
1 z> c
—1 .- .-
i~ p T r i-i
I FSP
I I -1 n
94
643
-7 --1 cr
1 CJ
1^ P T I--'
1 r '-' Tl
1 i_ ■_" LI
667
♦ ♦♦♦
N P T W F 'i'
1 Fi^Pi
X r Dn
1 114
667
N p T k' F =;
1 Ff.r.
1 115
1119
It FT 1
C 1 1
1 F 1^ M
X C ■_' 'J
943
945
1 T F T -'
1 FP Tl
943
955
1 FkPi
1 CO n
947
637
H P T A
1 F:-I7
963
944
I- n p p f
1 TirP.
341
71 1
p. f. s
1 PTlQ
71 1
679
upypl P
n c • 1 r
1 PPP
1 170
1 163
♦ ♦♦♦
c 3
3 1 4
J 1 ^
1-1 p V T Pi
n c I- -1 1 n
1 P J.;"'
i C "-r
9 -';-;
933
Q ■-' d
" ^
u p T Pi 1
n c "i 1 n 1
1 PSS
9 -1 3
931
1 7
-• c o
336
J. LI
1 "^PQ
107
14
T Ni' PT
1 1 04
7 03
T fj r p T I'
1 Ph^ Q
1 107
1 1 05
T (■■Jr i,,ipt;
i ' 1 - 1 C Z'
1 Ph
397
176
-Z' c O
( ' '_■
T Nri,,ip 1
i 1 V C X
L y ~ 1—
4
3 9 3
inn
fl |-| p q
O J
647
"y ;-. f 1
1 poo
966
6
6 n
T fj T T 1
1111 1 1
1 F ;-; f'
969
S 3 S
T NI
1 1 1L
M l"l F
U IJ 1 O
34
646
y~P'Zj
T NT'.i'FP
1111 V t b
1 y ^■c.
£31
133
1 OS
T p fi F N T
1 r-. C. M 1
1 PPP
1315
♦ ♦♦♦
T p fi P -y
1 P FP
1 P r C
519
♦ ♦♦♦
T P M T
1 i"' 1 F
i L X r
6 04
1315
I P IJ
1 7FF
113
6 04
k' F V T N
1 F71H
1 133
1 117
k'FV T N 1
• •■.CI 1 1 » L
1 F7r
X r 1 '_.
1 133
1 136
k'FV T N-'
X r •_• i_
1 137
1 134
1 '-. C 1 1 1 1 •_'
X r '_'n
1 133
1 136
k F V T M A
K C. 1 1 1 1 H
X r o LI
1135
1 133
1 n Pi Tl
1 I" F 7
r* c ■_'
r (_ 1
7 1—. i— '
1 Ol—
1 nwTlFP
1— U n i-l tl n.
1 Tl-'F
771
759
1 npriFi
1— u n L' c X
1 Ti-'p
X P
770
756
LJ n U
1 fPF
X ■_• c p.
1'' C Ct
♦ ♦♦♦
1 n M Ti T
L_ u nil I
1 o r" ■!<
133
331
1 n Pi ri T J.
1 ■-•p=:
1 D J
316
331
1 n Pi Tl T R
1 O Tl "7
X o LI r
C Z' -1'
£35
-1 •-■ -1
L l_l n L' 1 C'
1 opr
X '_' c L-
341
330
I— u n u 1 r
1 '-'PO
1 O f '_'
347
359
LDRDT3
1915
361
35
LDRLTy
1929
370
£53
£63
CROSS -REFEREHCE::
739 746
1154 1156
:5 1059 1179 lis
335 1066 1073 1153 1173 113
SYMBOL
VRLUE
LDflDV
lEi:i4
LORD 10
195E
LOflnu
18C£
LQHDia
lyiliF
LDRniS
13FR
LQRDa
IDOE
LnRiij
1 n 1 D
LORD?
iri£E
LORDS
IDS'iJ
MODE
UUFF
MOrilFY
1E15
HMIEMT
IFFR
NMIPP7
IBFR
\m I T
1 C 1 C
MMIV
17FR
□HE
199E
□HEKEV
IFijc'
OH El
1 9R 1
□ HE2
19Bri
□PEH
IFCC
□ UTET
1961
□ UTBTC
195E
□ UTCM
1 ER LI
□UTCHT
197R
□ UTSP
1E9E
□ UTl
1EB4
PRCK
IFRC
PRCKT
1 H
PRCKTl
1 R Lip
PRCKT2
1H15
prckt;:
lRc'£
pRnn
1741
PEnn
1743
pccMn
icnc
PCH
OF M
PCL
OOEF
PLLCRL
1R6B
PLLl
1R75
r LLc
1 no 4
P^IHTH
ijOPE
POIHTL
n ijFR
PREG
OF 1
PRTBVT
1E3E
PR TP NT
lElE
PRTST
1E31
PRTl
1E3R
RDEIT
1R41
RLEITa
1R53
RDEITS
1 R5
RriEIT4
1R63
RDBVT
19F3
RDBVTE'
19F9
RDCHT
lRc:4
RDCHTl
1R39
LI HE DEFIHED
CROSS-REFEREHCE?
374
369
371
£63
C C -Z'
£ 1 8
cr o
13£
■-1 .A -1
c _i4
746
751
754
744
764
♦ ♦♦♦
765
91
r I' c
636
7 05
967
334
£;63
1 £ 1 3
♦♦♦♦
517
♦♦♦♦
6 03
1£13
1 1 1
6 03
353
336
339
1 04
1116
■J" ■_•
356
363
36 1
36 c
1 135
796
8£8
3 9
141
15.7
159
3 3
144
146
174
934
1*' "Z" i''
91
934
13£
133
155
933
331
335
993
9 9 9
1 164
651
1 155
1 157
413
£51
4 05
4 07
421
413
436
4 £9
433
414
416
59
97
1 061
1 079
61
1£3
496
97£
717
671
i''
594
719
i' C
591
717
493
517
518
519
493
499
511
5 05
5 06
C' r'
36
1 7
1 1 06
169
C 1'' c
1 188
£71
595
59£
31£
345
74
539
847
917
795
3
3 0£
397
797
3 09
33 U
9 09
64 £
767
91 £
9 1 3
♦ ♦♦♦
457
£
441
458
467
468
464
465
476
477
4 04
'Z' -Z" 'Z'
l_ ■_' ■_•
£36
4 6
♦ ♦♦♦
439
£09
£16
£43
441
446
164
69 1
879
813
69.
713
9 1]
;£0
£41 £45
£61
?64
StMEOL
VhLUE
LINE DEFINED
r
RDSS-
REFERENCES
READ
1C6R
64 S
87
RST
1 CE'£
6 1 j 6
1814
R STENT
IFFC
1214
♦♦♦♦
RSTP£7
1 EEC
518
+ ♦+ +
RSTV
1 7FC
1 1£
♦ ♦♦♦
RTRM
IDCc
888
859
c' r'
s.Rn
174
C 1-1
1-1
615
6£3
6 38
66
943
943
1 044
1 089
3RH
1 7F6
1 04
145
883
SRL
17F5
1 08
143
£81
SRVE
1 C U IJ
587
SRVEl
1 C 5
59
SRVEE
1 IS F
596
♦♦♦♦
SRVX
1 7E9
98
1 98
£01
£ 0£
£ 03
£04
33 :l
334
345
48
439
448
443
444
448
451
SEIi
174c:
6
186
195
36
Si 6' 6
•
I-! 9
457
467
5 1
766
974
987
9 8 9
9 98
99 h
1 Ij
1 049
1 077
1 09 Ij
SCRN
1 DDE
854
658
SCRHIi
1 F 1 9
1 057
657
66 £
664
SCRN US
1 Fl F
1 06
♦ ♦♦♦
SCRNDl
IFE'S
1 066
1 076
SHOW
1 DRC
Sc9
R ! -i 9
888
SHDl.Jl
1 riRF
3 8
648
SPRCE
1 riR9
8c 8
855
SPUSER
U 0F£
1 _■
599
6 8
841
STRRT
1C4F
6 8 6
171
c r' Z'
6 1
6 1 6
6 5 8
661
669
7 06
763
O I' c
STEP
1CD3
7 08
677
STV
IDFE
C" i"' C
1-1 cr -7
o _i r
SYNC
1 S'3 1
197
£11
££0
SVNCl
1896
£
£ 06
SYNC 2
1 RRE
8 09
£ 1 8
TRE
1 R7 1
188
189
191
TRELE
1FE7
1 c 08
1 087
TEMP
UFC
684
689
917
9 8 3
985
1 085
1 099
T I m
17F4
108
1011
1 1 6
1017
1 0£3
1 086
TMPX
OFE
89
94
953
985
1 nu4
TDP
lFri5
1 197
9 09
TTYKE
1C77
657
689
65
TTYKEl
1C7C
659
6 6 Si
665
LIPDRTE
IFEE
1 178
1 1 69
UPBRTl
1 FC 1
1 177
1181
iJPDRTc
IFCE
1 188
1 165
1 167
VEE
17EC
99
1££
143
150
173
184
1 PiiEi
1 9
1 98
£57
C 'C' c
£34
£86
397
3 99
XREb
i:iOF4
i' 1''
597
349
YREG
OOF 5
r' y
596
85
ZRD
19C4
876
841
34 £
1 091
346 487
4 94
1 08
5 3
1 041
7 1 j 9
INSTRUCT I Dh CDUHT
O Ti i~
rf U L.
1 •
nil U
Cl I
MiL
T' r- 1~
C i~i
£6
T« T X
b 1 r
1 c
EMI
BhE
44
br L
1
b r r--.
IJ
b V L
IJ
b V -2-
LLL-
IJ
L-LLI
1
r-i T
1.1
P 1 '. '
L- L V
l_l
L I Ir
l"' c« v
1
Lr 1
tj
Ti C I'-
ll t'_-
c!
Uh,--,
1 4
i't 1
'"'
t UK
d
T Ml"
r
1 ri--.
c
T M'.-'
c
•Jnr
■ 1
I r-r-"
•J
1 1
1 TiiZi
1 Uo
1 Ti '■ •'
L.LK-;
c9
1 Ti '.
-1 cr
C
hj n Cl
noiZi
IJKH
r Hrl
c
Cl Lj r"i
F HP
F LH
r Lr
r. UL
1 o
K 1 i
1
r, 1 i
-■• bL-
c-
■r- r- 1-.
ib-L
'-'
■~ C Ti
IJ
■r- r- T
1
•r- xci
j- 1 H
o 1
1 4
r"
T iZi
•-'
THt
TSX
1
TXR
T>^x
c
TV'H
4
SYMBOLS = £04 c LI MIT = 4 0;' - BYTES = 169 (LIMIT = 4 09
LIMES = lE:4c: (LIMIT = 1500;' " KREFS = 64t. (LIMIT = 900;;'
MOSTECHNOLOGY INC
VALLEY FORGE CORPORATE CENTER
950 RITTENHOUSE ROAD. NORRISTOWN, PA. 19401
TEL: (215) 666-7950 TWX :61 0/660/4033
Live Music
Archive
Librivox
Free Audio
Metropolitan Museum
Cleveland
Museum of Art
Internet
Arcade
Console Living Room
Open Library
American
Libraries
TV News
Understanding
9/11